ICS83947AYI-147 ICST [Integrated Circuit Systems], ICS83947AYI-147 Datasheet

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ICS83947AYI-147

Manufacturer Part Number
ICS83947AYI-147
Description
LOW SKEW, 1-TO-9 LVCMOS/LVTTL FANOUT BUFFER
Manufacturer
ICST [Integrated Circuit Systems]
Datasheet

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G
series or parallel terminated transmission lines. The effective
fanout can be increased from 9 to 18 by utilizing the ability of
the outputs to drive two series terminated lines.
Guaranteed output and part-to-part skew characteristics make
the ICS83947I-147 ideal for high performance, 3.3V or 2.5V
single ended applications.
CLK_SEL
83947AYI-147
B
HiPerClockS™
CLK_EN
ICS
ENERAL
LOCK
CLK0
CLK1
OE
The ICS83947I-147 is a low skew, 1-to-9
LVCMOS/LVTTL Fanout Buffer and a member of
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The low impedance
LVCMOS/LVTTL outputs are designed to drive 50Ω
D
IAGRAM
0
1
Integrated
Circuit
Systems, Inc.
D
ESCRIPTION
D
LE
Q
http://www.icst.com/products/hiperclocks.html
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
1
P
F
• 9 LVCMOS/LVTTL outputs
• Selectable CLK0 and CLK1 can accept the following
• Maximum output frequency: 250MHz
• Output skew: 115ps (maximum)
• Part-to-part skew: 500ps (maximum)
• Additive phase jitter, RMS: 0.02ps (typical) @ 3.3V
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Pin compatible with the MPC947
input levels: LVCMOS and LVTTL
IN
EATURES
CLK_SEL
CLK_EN
A
CLK0
CLK1
GND
GND
V
SSIGNMENT
OE
DD
LVCMOS/LVTTL F
7mm x 7mm x 1.4mm package body
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
ICS83947I-147
32-Lead LQFP
Y Package
Top View
ICS83947I-147
L
OW
REV. A SEPTEMBER 24, 2004
ANOUT
S
24
23
22
21
20
19
18
17
KEW
GND
Q3
V
Q4
GND
Q5
V
GND
DDO
DDO
, 1-
B
UFFER
TO
-9

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ICS83947AYI-147 Summary of contents

Page 1

Integrated Circuit Systems, Inc ENERAL ESCRIPTION The ICS83947I-147 is a low skew, 1-to-9 ICS LVCMOS/LVTTL Fanout Buffer and a member of HiPerClockS™ the HiPerClockS™ family of High Performance Clock Solutions from ICS. The low impedance LVCMOS/LVTTL outputs are ...

Page 2

Integrated Circuit Systems, Inc ABLE IN ESCRIPTIONS ...

Page 3

Integrated Circuit Systems, Inc BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs, V -0. Package Thermal Impedance, θ JA Storage Temperature, T -65°C to 150°C STG T 4A. ...

Page 4

Integrated Circuit Systems, Inc ABLE HARACTERISTICS ...

Page 5

Integrated Circuit Systems, Inc. The spectral purity in a band at a specific offset from the funda- mental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise ...

Page 6

Integrated Circuit Systems, Inc. P ARAMETER 1.65V ± 0.15V DDO LVCMOS GND -1.65V ± 0.15V 3. UTPUT OAD EST IRCUIT PART 1 V DDO Qx 2 PART 2 V DDO Qy ...

Page 7

Integrated Circuit Systems, Inc PPLICATION CHEMATIC XAMPLE Figure 1 shows an example of ICS83947I-147 application sche- matic. In this example, the device is operated at V decoupling capacitors should be located as close as possible to the ...

Page 8

Integrated Circuit Systems, Inc. θ ABLE VS IR LOW ABLE FOR JA θ θ θ θ θ Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs ...

Page 9

Integrated Circuit Systems, Inc ACKAGE UTLINE UFFIX FOR ABLE ACKAGE ...

Page 10

Integrated Circuit Systems, Inc ABLE RDERING NFORMATION ...

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