AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 76

• Manufacturer Part Number: AMD-766AC
• Description: Peripheral Bus Controller
• Manufacturer: AMD [Advanced Micro Devices]

23167B – March 2001
PM30: Miscellaneous SMI Status Register
IO mapped (base pointer: C3A58); offset: 31-30h. Default: 0000h. Read; set by hardware; write 1 to clear.
Each of these status bits may be enabled to generate SMI interrupts via PM32.
15
Reserved
7
Reserved
SLPCMD_STS. Sleep command status. 1=A write occurred to PM04 with bit[13], SLP_EN, set high.
RWR_STS. BIOS ROM write enable status. 1=C0A40[RWR] was written from a 0 to a 1.
SIRQSMI_STS. Serial IRQ SMI status. 1=SMI interrupt was initiated from the serial IRQ logic from the SERIRQ
pin.
1MIN_STS. One minute status bit. 1=One minute expired. After entering the FON state, this bit is set every 60 +/-
4 seconds.
64MS_STS. 64 millisecond timer status. 1=64 milliseconds expired. After PM32[64MS_EN] is set high, the 64
millisecond timer sets this bit every 64 +/- 4 milliseconds. The timer does not stop after this bit is set.
PM32: Miscellaneous SMI Enable Register
IO mapped (base pointer: C3A58); offset: 33-32h. Default: 0000h.
For each of the bits in this register: 1=enable a corresponding status bit in PM30 to generate an SMI interrupt. 0=Do
not enable the SMI interrupt.
15
Reserved
7
Reserved
SLPCMD_EN. Enable SMI on sleep command. Read-write. Note: When this bit is high and the sleep command is
sent to PM04, the system power state is disabled from changing. It is expected that the SMI interrupt service routine
clears PM30[SLPCMD_STS], clears this bit, and then re-issues the command in order to change the power state.
RWR_EN. BIOS ROM write enable SMI enable. Read, write to 1 only. Once this bit is set, it may only be cleared
by PCIRST#.
SIRQSMI_EN. Serial IRQ SMI enable. Read-write.
1MIN_EN. One minute SMI enable. Read-write.
64MS_EN. 64 millisecond SMI enable. Read-write. 1=Enable PM32[64MS_STS] to generate SMI interrupts and
enable the 64 millisecond timer. 0=The 64 millisecond timer is cleared.
PM38: IO Cycle Tracker Register
IO mapped (base pointer: C3A58); offset: 3B-38h. Default: 0000_0000h. Read only.
31:20
Reserved
TDRADDR. Tracker address. Contains the lower 16 bits of the PCI bus address phase for the last transaction before
SMI was asserted. This may be used to determine the IO access that triggered an SMI.
TDRCMD. Tracker command. Contains the PCI bus command for the last transaction before SMI was asserted.
PM40: TCO Timer Reload and Current Value Register
IO mapped (base pointer: C3A58); offset: 40h. Default: 04h. Read; write command.
The TCO timer is a 6-bit down counter that is clocked approximately every 0.6 seconds providing times of up to 38
seconds. If it counts past zero, PM44[TOUT_STS] is set, the timer rolls over to the value in PM41, and the timer
continues counting.
7:6
Reserved
TCORLD. TCO timer. Reads from this register return the current count of the TCO timer. Writes of any value
cause the TCO timer to be reloaded with the value in PM41.
14
Reserved
6
Reserved
14
Reserved
6
Reserved
13
Reserved
5
Reserved
13
Reserved
5
Reserved
5:0
TCORLD
12
Reserved
4
64MS_STS
12
Reserved
4
64MS_EN
19:16
TKRCMD
Preliminary Information
11
Reserved
3
1MIN_STS
11
Reserved
3
1MIN_EN
15:0
TKRADDR
AMD-766
10
Reserved
2
SIRQSMI_STS
10
Reserved
2
SIRQSMI_EN
TM
Peripheral Bus Controller Data Sheet
Reserved
RWR_STS
Reserved
RWR_EN
9
1
9
1
8
Reserved
0
SLPCMD_STS
8
Reserved
0
SLPCMD_EN
76