AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 81

• Manufacturer Part Number: AMD-766AC
• Description: Peripheral Bus Controller
• Manufacturer: AMD [Advanced Micro Devices]

23167B – March 2001
Bit[7] CMB_TRP_RLEN. Serial port B (COM B) access trap causes reload of system inactivity timer.
Bit[8] AUD_TRP_RLEN. Audio functions access trap causes reload of system inactivity timer.
Bit[9] VID_TRP_RLEN. Video functions access trap causes reload of system inactivity timer.
Bit[10] KBM_TRP_RLEN. Keyboard and mouse access trap causes reload of system inactivity timer.
Bit[11] PCMCIA1_TRP_RLEN. PCMCIA1 access trap causes reload of system inactivity timer.
Bit[12] PCMCIA2_TRP_RLEN. PCMCIA2 access trap causes reload of system inactivity timer.
Bit[13] USB_TRP_RLEN. USB access or activity trap causes reload of system inactivity timer.
Bit[14] PRM1_TRP_RLEN. Programmable range monitor 1 access trap causes reload of system inactivity timer.
Bit[15] PRM2_TRP_RLEN. Programmable range monitor 2 access trap causes reload of system inactivity timer.
Bit[16] PRM3_TRP_RLEN. Programmable range monitor 3 access trap causes reload of system inactivity timer.
Bit[17] PRM4_TRP_RLEN. Programmable range monitor 4 access trap causes reload of system inactivity timer.
Bit[18] PMM1_TRP_RLEN. Programmable memory range monitor 1 access trap causes reload of system inactivity
timer.
Bit[19] PMM2_TRP_RLEN. Programmable memory range monitor 2 access trap causes reload of system inactivity
timer.
Bit[20] EXTSMI_RLEN. 1=Assertion of PM20[EXSMI_STS] causes a reload of the system inactivity timer. Note:
As long as the status bit is set, the system inactivity timer is held in its reload value and does not decrement.
Bit[21] BMREQ_RLEN. 1=Assertion of a PCI bus master request causes a reload of the system inactivity timer.
PMB4: IRQ Reload Enable For System Inactivity Timer Register
IO mapped (base pointer: C3A58); offset: B7-B4h. Default: 0000_0000h. Read-write.
31:16
Reserved
IRQRL. IRQs reload the system inactivity timer. Each of these bits corresponds its bit number to an IRQ number to
the legacy PIC (e.g., bit[12] corresponds to IRQ12). The exception to this is bit[2], which corresponds to the INTR
pin, output of the legacy PIC. 1=Enable the corresponding interrupt signal to cause the system inactivity timer to
reload when it transitions. 0=Do not affect the system inactivity timer.
Preliminary Information
15:0
IRQRL
AMD-766
TM
Peripheral Bus Controller Data Sheet
81