APA075-FG896A ACTEL [Actel Corporation], APA075-FG896A Datasheet

APA075-FG896A

Manufacturer Part Number

APA075-FG896A

Description

Automotive-Grade ProASIC Flash Family FPGAs

Manufacturer

ACTEL [Actel Corporation]

Datasheet

1.APA075-FG896A.pdf (10 pages)

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Automotive-Grade ProASIC

Features and Benefits

High Capacity

•

Reprogrammable Flash Technology

•

Extended Temperature Range

•

Performance

•

Secure Programming

•

Low Power

•

High Performance Routing Hierarchy

•

Table 1 • Automotive-Grade ProASIC

February 2004

Device

Maximum System Gates

Maximum Tiles (Registers)

Embedded RAM Bits (k=1,024

bits)

Embedded RAM Blocks (256x9)

LVPECL

PLL

Global Networks

Maximum Clocks

Maximum User I/Os

JTAG ISP

PCI

Package (by pin count)

TQFP

PQFP

FBGA

75,000 to 1 Million System Gates

27k to 198kbits of Two-Port SRAM

66 to 642 User I/Os

0.22 4LM Flash-based CMOS Process

Live at Power-Up, Single-Chip Solution

No Configuration Device Required

Retains Programmed Design during

Power-Down/Power-Up Cycles

Supports Automotive Temperature Range -40 to 125°C (Junction)

3.3V, 32-Bit PCI (up to 50 MHz)

Two Integrated PLLs

External System Performance up to 150 MHz

Industry’s Most Effective Security Key (FlashLock™)

Prevents Read Back of Programming Bitstream

Low Impedance Flash Switches

Segmented Hierarchical Routing Structure

Small, Efficient, Configurable (Combinatorial or Sequential)

Logic Cells

Ultra-Fast Local and Long-Line Network

APA075

PLUS

75,000

3,072

27k

158

100

208

144

Yes

Product Profile

APA150

144, 256

150,000

6,144

186

100

36k

208

Yes

PLUS

APA300

144, 256

300,000

8,192

72k

186

208

Yes

•

I/O

•

Unique Clock Conditioning Circuitry

•

Standard FPGA and ASIC Design Flow

•

ISP Support

•

SRAMs and FIFOs

•

–

High-Speed, Very Long-Line Network

High Performance, Low-Skew, Splittable Global Network

100% Utilization and >95% Routability

Schmitt-Trigger Option on Every Input

2.5V/3.3V Support with Individually-Selectable Voltage and

Slew Rate

Bidirectional Global I/Os

Compliance with PCI Specification Revision 2.2

Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant

Pin Compatible Packages across ProASIC

PLLs with Flexible Phase, Multiply/Divide and Delay

Capabilities

Internal and/or External Dynamic PLL Configuration

Two LVPECL Differential Pairs for Clock or Data Inputs

Flexibility with Choice of Industry-Standard Frontend Tools

Efficient Design through Front-End Timing and Gate

Optimization

In-System Programming (ISP) via JTAG Port

ACTgen Netlist Generation Ensures Optimal Usage of

Embedded Memory Blocks

24 SRAM and FIFO Configurations with Synchronous and

Asynchronous Operation up to 150 MHz (typical)

Flash Family FPGAs

144, 256, 484

APA450

450,000

12,288

108k

344

208

Yes

–

APA600

256, 484

600,000

21,504

Automotive Supplement

126k

370

208

Yes

–

APA750

750,000

32,768

144k

562

208

Yes

896

PLUS

–

Family

APA1000

1,000,000

56,320

198k

642

208

896

Yes

–

Related parts for APA075-FG896A

APA075-FG896A Summary of contents

Page 1

... In-System Programming (ISP) via JTAG Port SRAMs and FIFOs • ACTgen Netlist Generation Ensures Optimal Usage of Embedded Memory Blocks • 24 SRAM and FIFO Configurations with Synchronous and Asynchronous Operation up to 150 MHz (typical) PLUS Product Profile APA075 APA150 APA300 75,000 150,000 300,000 3,072 6,144 8,192 27k ...

Page 2

... APA075 APA150 APA300 APA450 APA600 APA750 APA1000 Plastic Device Resources TQFP Device 100-Pin APA075 66 APA150 66 APA300 APA450 APA600 APA750 APA1000 Package Definitions TQFP = Thin Quad Flat Pack, PQFP = Plastic Quad Flat Pack, FBGA = Fine Pitch Ball Grid Array *Each pair of PECL I/Os were counted as one user I/O. ...

Page 3

General Description PLUS ProASIC devices offer a reprogrammable design integration solution at the automotive temperature range (-40°C to +125°C) through the use of nonvolatile PLUS Flash technology. ProASIC devices have a fine-grain architecture, similar to ASICs, and enable engineers to ...

Page 4

PLUS Automotive-Grade ProASIC Flash Family FPGAs Operating Conditions Table 1 • Absolute Maximum Ratings* Parameter Supply Voltage Core ( Supply Voltage I/O Ring (V ) DDP DC Input Voltage PCI DC Input Voltage PCI DC Input Clamp Current ...

Page 5

Table 2 • Performance Retention Time at T 110°C or below J 100% 99% 98% 95% 90% 85% 80% 75% 70% 60% 50% 25% 0% Table 3 • Nominal Supply Voltages Mode 2.5V Output 3.3V Output* PLUS Note: *Automotive-grade ProASIC ...

Page 6

PLUS Automotive-Grade ProASIC Flash Family FPGAs Table 5 • Recommended Operating Conditions* Parameter DC Supply Voltage (2.5V I/Os) DC Supply Voltage (3.3V I/Os) Operating Junction Temperature Range Note: *Devices should not be operated outside the Recommended Operating Conditions. Table 6 ...

Page 7

Table 7 • DC Electrical Specifications (V Symbol Parameter V Output High Voltage OH 3.3V I/O, High Drive (OB33P) 3.3V I/O, Low Drive (OB33L) V Output Low Voltage OL 3.3V I/O, High Drive (OB33P) 3.3V I/O, Low Drive (OB33L) V ...

Page 8

PLUS Automotive-Grade ProASIC Flash Family FPGAs Table 8 • DC Specifications (3.3V PCI Revision 2.2 Operation) Symbol Parameter V Supply Voltage for Core DD V Supply Voltage for I/O Ring DDP V Input High Voltage IH V Input Low Voltage ...

Page 9

Table 9 • AC Specifications (3.3V PCI Revision 2.2 Operation) Symbol Parameter Condition I Switching Current High 0 < V OH(AC) 0.3V 0.7V (Test Point) V OUT I Switching Current Low V OL(AC) CCI 0.6V 0.18V (Test Point) V OUT ...

Page 10

Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation Actel Europe Ltd. 2061 Stierlin Court Dunlop House, Riverside Way Mountain View, CA Camberley, Surrey GU15 3YL 94043-4655 ...

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