CAT24C043 CATALYST [Catalyst Semiconductor], CAT24C043 Datasheet
CAT24C043
Related parts for CAT24C043
CAT24C043 Summary of contents
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... Advanced CAT24C163(16K), CAT24C083(8K) CAT24C043(4K), CAT24C023(2K) Supervisory Circuits with Serial CMOS E 2 PROM, Precision Reset Controller and Watchdog Timer FEATURES Watchdog Timer Input (WDI) Programmable Reset Threshold 400 KHz Bus Compatible 2 Volt Operation Low Power CMOS Technology 16 - Byte Page Write Buffer Built-in inadvertent write protection — ...
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ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias....................– +125 C Storage Temperature........................ – +150 C Voltage on Any Pin with (1) Respect to Ground ..............–2. with Respect to Ground..................–2.0V to +7.0V CC Package Power Dissipation ...
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Advanced A.C. CHARACTERISTICS V =2.7V to 6.0V unless otherwise specified. CC Output Load is 1 TTL Gate and 100pF Read & Write Cycle Limits Symbol Parameter F Clock Frequency SCL (1) T Noise Suppression Time I Constant at SCL, SDA ...
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RESET CIRCUIT CHARACTERISTICS Symbol Parameter t Glitch Reject Pulse Width GLITCH V Reset Threshold Hystersis RT V Reset Output Low Voltage (I OLRS V Reset Output High Voltage OHRS Reset Threshold (Vcc=5V) (24CXXX-45) Reset Threshold (Vcc=5V) (24CXXX-42) Reset Threshold (Vcc=3.3V) ...
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Advanced PIN DESCRIPTIONS WDI: WATCHDOG INPUT If there is no transition on the WDI for more than 1.6 seconds, the watchdog timer times out. WP: WRITE PROTECT If the pin is tied to V the entire memory array becomes CC ...
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CAT24C163/083/043/023 Hardware Data Protection The 24CXXX is designed with the following hardware data protection features to provide a high degree of data integrity. (1) The 24CXXX features a WP pin. When WP pin is tied high the entire memory array ...
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Advanced FUNCTIONAL DESCRIPTION 2 The CAT24CXXX supports the I sion protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus transmitter and any device receiving data re- ceiver. The ...
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CAT24C163/083/043/023 ACKNOWLEDGE After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledg- ing device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The ...
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Advanced Acknowledge Polling Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation, CAT24CXXX initiates the internal write cycle. ...
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CAT24C163/083/043/023 Immediate/Current Address Read The CAT24CXXX’s address counter contains the ad- dress of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would ac- ...
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Advanced Ordering Information Prefix Device # CAT Optional Product Company ID Number 24C163: 16K 24C083: 8K 24C043: 4K 24C023 -40˚ to +125˚C is available upon request Note: (1) The device used in ...
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Doc. No. 25080-00 3/98 M-1 12 Advanced ...