CAT93C57 CATALYST [Catalyst Semiconductor], CAT93C57 Datasheet - Page 8

• Manufacturer Part Number: CAT93C57
• Description: 2-Kb Microwire Serial CMOS EEPROM
• Manufacturer: CATALYST [Catalyst Semiconductor]

CAT93C56, CAT93C57
Write
After receiving a WRITE command (Figure 4), address
and the data, the CS (Chip Select) pin must be
deselected for a minimum of t
CS will start the self clocking clear and data store cycle
of the memory location specified in the instruction. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the CAT93C56/57 can be determined by
selecting the device and polling the DO pin. Since this
device features Auto-Clear before write, it is NOT
necessary to erase a memory location before it is
written into.
Figure 4. Write Instruction Timing
Figure 5. Erase Instruction Timing
Doc. No. MD-1088 Rev. P
DO
CS
SK
DO
CS
DI
SK
DI
1
1
0
1
1
1
CSMIN
A N
. The falling edge of
A N
A N-1
A N-1
HIGH-Z
HIGH-Z
A 0
8
D N
A 0
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a
minimum of t
start the self clocking clear cycle of the selected
memory location. The clocking of the SaK pin is not
necessary after the device has entered the self clocking
mode. The ready/busy status of the CAT93C56/57 can
be determined by selecting the device and polling the
DO pin. Once cleared, the content of a cleared location
returns to a logical “1” state.
D 0
CSMIN
t SV
t SV
(Figure 5). The falling edge of CS will
t EW
t EW
t CSMIN
STATUS VERIFY
t CS
BUSY
STATUS
VERIFY
BUSY
Characteristics subject to change without notice
READY
READY
© Catalyst Semiconductor, Inc.
HIGH-Z
STANDBY
STANDBY
t HZ
HIGH-Z
t HZ