AD8332 AD [Analog Devices], AD8332 Datasheet - Page 25

• Manufacturer Part Number: AD8332
• Description: Ultralow Noise VGAs with Preamplifier and Programmable RIN
• Manufacturer: AD [Analog Devices]

43.5
–4.5
The previously mentioned clamp interface controls the
maximum output swing of the postamp and its overload
response. When no R
to near 4.5 V p-p differential to protect outputs centered at a
2.5 V common mode. When other common-mode levels are set
through the VCM pin, the value of R
graceful overload. A value of 8.3 kΩ or less is recommended for
1.5 V or 3.5 V common-mode levels (7.2 kΩ for HI gain mode).
This limits the output swing to just above 2 V p-p diff.
OPTIONAL INPUT OVERLOAD PROTECTION.
Applications in which high transients are applied to the LNA
input may benefit from the use of clamp diodes. A pair of back-
to-back Schottky diodes can reduce these transients to
manageable levels. Figure 73 illustrates how such a diode-
protection scheme may be connected.
When selecting overload protection, the important parameters
are forward and reverse voltages and t
BAS40 series shown in Figure 73 has a τ
310 mV at 1 mA. Many variations of these specifications can be
found in vendor catalogs.
1m
OVERLOAD
POSTAMP
INPUT AMPLITUDE (V)
15mV
OVERLOAD
SCHOTTKY
2
10m
OPTIONAL
LO GAIN
BAS40-04
MODE
CLAMP
3
Figure 72. Overload Gain and Signal Conditions
OVERLOAD
25mV
1
X-AMP
0.1
FB
Figure 73. Input Overload Clamping
.275
CLMP
0.1µF
1
29dB
24.5dB
resistor is provided, this level defaults
C
R
SH
SH
56.5
7.5
C
1m
R
FB
OVERLOAD
FB
POSTAMP
CLMP
4mV
rr
INPUT AMPLITUDE (V)
(or τ
rr
10m
HI GAIN
should be chosen for
MODE
of 100 ps and V
2
3
4
OVERLOAD
rr
25mV
INH
VPS
LON
.). The Infineon
X-AMP
0.1
COMM
ENBL
0.275
1
41dB
24.5dB
20
19
F
of
Rev. C | Page 25 of 32
LAYOUT, GROUNDING, AND BYPASSING
Due to their excellent high frequency characteristics, these
devices are sensitive to their PCB environment. Realizing
expected performance requires attention to detail critical to
good high speed board design.
A multilayer board with power and ground plane is
recommended, and unused area in the signal layers should be
filled with ground. The multiple power and ground pins provide
robust power distribution to the device and must all be
connected. The power supply pins should each be with multiple
values of high frequency ceramic chip capacitors to maintain
low impedance paths to ground over a wide frequency range.
These should have capacitance values of 0.01 μF to 0.1 μF in
parallel with 100 pF to 1 nF, and be placed as close as possible to
the pins. The LNA power pins should be decoupled from the
VGA using ferrite beads. Together with the decoupling
capacitors, ferrite beads help eliminate undesired high
frequencies without reducing the headroom, as do small value
resistors.
Several critical LNA areas require special care. The LON and
LOP output traces must be as short as possible before
connecting to the coupling capacitors connected to Pins VIN
and VIP. R
Resistors must be placed as close as possible to the VGA output
pins VOL and VOH to mitigate loading effects of connecting
traces. Values are discussed in the section entitled Output
Filtering and Series Resistor
Requirements.
Signal traces must be short and direct to avoid parasitic effects.
Wherever there are complementary signals, symmetrical layout
should be employed to maintain waveform balance. PCB traces
should be kept adjacent when running differential signals over a
long distance.
MULTIPLE INPUT MATCHING
Matching of multiple sources with dissimilar impedances can
be accomplished as shown in the circuit of Figure 75. A relay
and low supply voltage analog switch may be used to select
between multiple sources and their associated feedback
resistors. An ADG736 dual SPDT switch is shown in this
example; however, multiple switches are also available and users
are referred to the Analog Devices Selection Guide for switches
and multiplexers.
DISABLING THE LNA
Where accessible, connection of the LNA enable pin to ground
will power down the LNA, resulting in a current reduction of
about half. In this mode, the LNA input and output pins may be
left unconnected, however the power must be connected to all
the supply pins for the disabling circuit to function. Figure 74
illustrates the connections using an AD8331 as an example.
FB
must be placed nearby the LON pin as well.
AD8331/AD8332