PCF85102C-2T PHILIPS [NXP Semiconductors], PCF85102C-2T Datasheet - Page 8

• Manufacturer Part Number: PCF85102C-2T
• Description: 256 x 8-bit CMOS EEPROMs with I2C-bus interface
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
8.3
Following a START condition, the bus master must output
the address of the slave it is accessing. The four MSBs of
the slave address are the device type identifier (see Fig.4
and Fig.5). For the PCF85102C-2, this is fixed to ‘1010’,
for the PCF85103C-2 to ‘0010’.
The next three significant bits address a particular device
or memory page (page = 256 bytes of memory). A system
could have up to sixteen PCF8510xC-2 devices on the
bus. This can be achieved with eight PCF85102C devices
and eight PCF85103C devices, combined on one I
The eight addresses are defined by the state of the A0, A1
and A2 inputs per type.
The last bit of the slave address defines the operation to
be performed. When set to logic 1, a read operation is
selected.
Address bits must be connected to either V
8.3.1
The I
reserved for device PCF85103C-2. Therefore, multiple
use has to be checked in advance.
2000 Feb 15
handbook, halfpage
handbook, halfpage
256
I
2
C-bus interface
2
C-bus device select address ‘0010’ is not exclusively
Device addressing
Fig.4 Slave address for PCF85102C-2.
Fig.5 Slave address for PCF85103C-2.
R
EMARK
8-bit CMOS EEPROMs with
0
1
0
0
1
1
0
0
A2
A2
A1
A1
A0 R/W
A0 R/W
MGL970
MBC793
DD
or V
2
SS
C-bus.
.
8
8.4
8.4.1
For a write operation, the PCF8510xC-2 requires a second
address field. This address field is a word address
providing access to the 256 words of memory. On receipt
of the word address, the PCF8510xC-2 responds with an
acknowledge and awaits the next eight bits of data, again
responding with an acknowledge. The word address is
automatically incremented. The master can now terminate
the transfer by generating a STOP condition or
transmitting up to six more bytes of data and then
terminating by generating a STOP condition.
After this STOP condition, the E/W cycle starts and the bus
is free for another transmission. The duration of the
E/W cycle is 10 ms per byte.
During the E/W cycle, the slave receiver does not send an
acknowledge bit if addressed via the I
8.4.2
The PCF8510xC-2 is capable of an 8-byte page write
operation. It is initiated in the same manner as the byte
write operation. The master can transmit eight data bytes
within one transmission. After receipt of each byte, the
PCF8510xC-2 will respond with an acknowledge.
The typical E/W time in this mode is 9
Erasing a block of eight bytes in page mode takes a typical
3.5 ms and sequential writing of these eight bytes another
typical 28 ms.
After the receipt of each data byte, the three low order bits
of the word address are internally incremented. The five
high order bits of the address remain unchanged.
The slave acknowledges the reception of each data byte
with an ACK. The I
the master after the eighth byte with a STOP condition.
If the master transmits more than eight bytes prior to
generating the STOP condition, no acknowledge will be
given on the ninth (and following) data bytes. Also, the
whole transmission will be ignored and no programming
will be done. As in the byte write operation, all inputs are
disabled until completion of the internal write cycles.
Write operations
B
P
PCF85102C-2; PCF85103C-2
YTE
AGE WRITE
/
WORD WRITE
2
C-bus data transfer is terminated by
Product specification
2
C-bus.
3.5 ms = 31.5 ms.