74LVC544 PHILIPS [NXP Semiconductors], 74LVC544 Datasheet - Page 2

• Manufacturer Part Number: 74LVC544
• Description: Octal D-type registered transceiver, inverting 3-State
• Manufacturer: PHILIPS [NXP Semiconductors]

1. C
2. The condition is V
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0V; T
NOTES:
ORDERING AND PACKAGE INFORMATION
t
C
C
C
24-Pin Plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
1998 Jul 29
PHL
Wide supply voltage range of 1.2V to 3.6V
In accordance with JEDEC standard no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
Combines 74LVC640 and 74LVC533 type functions in one chip
Octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
3-State inverting outputs for bus oriented applications
5 Volt tolerant inputs/outputs, for interfacing with 5 Volt logic
Octal D-type registered transceiver, inverting
(3-State)
I
I/O
PD
P
f
f
i
o
PD
D
= input frequency in MHz; C
/t
(C
= output frequency in MHz; V
PLH
= C
SYMBOL
L
is used to determine the dynamic power dissipation (P
PACKAGES
PD
V
amb
CC
V
2
= 25 C; t
CC
2
f
I
o
x f
= GND to V
) = sum of the outputs.
i
r
Propagation delay
An to Bn
Input capacitance
Input/output capacitance
Power dissipation capacitance per latch
) (C
= t
f
v2.5 ns
TEMPERATURE RANGE
L
L
CC.
= output load capacitance in pF;
CC
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
V
= supply voltage in V;
CC
PARAMETER
2
f
o
) where:
D
OUTSIDE NORTH
in W)
74LVC544A PW
74LVC544A DB
74LVC544A D
AMERICA
C
V
Notes 1, 2
L
CC
2
= 50pF
= 3.3V
DESCRIPTION
The 74LVC544A is a high performance, low-power, low-voltage
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC544A is an octal registered inverting transceiver
containing two sets of D-type latches for temporary storage of the
data flow in either direction. Separate latch enable (LEAB, LEBA)
and output enable (OEAB, OEBA) inputs are provided for each
register to permit independent control of inputting and outputting in
either direction of the data flow.
The ‘544A’ contains eight D-type latches with separate inputs and
controls for each set. For data flow from A to B, for example, the
A-to-B enable (EAB) input must be LOW in order to enter data from
A0–A7 or take data from B0–B7, as indicated in the function table.
With EAB LOW, a LOW signal on the A-to-B latch enable (LEAB)
input makes the A-to-B latches transparent; a subsequent
LOW-to-HIGH transition of the LEAB signal puts the A data into the
latches where it is stored and the B outputs no longer change with
the A inputs. With EAB and OEAB both LOW, the 3-State B output
buffers are active and display the data present at the outputs of the
A latches.
CONDITIONS
NORTH AMERICA
7LVC544APW DH
74LVC544A DB
74LVC544A D
TYPICAL
5.0
10
30
4
74LVC544A
Product specification
PKG. DWG. #
SOT137-1
SOT340-1
SOT355-1
853-2107 19804
UNIT
pF
pF
pF
ns