74LVC573 PHILIPS [NXP Semiconductors], 74LVC573 Datasheet - Page 2

• Manufacturer Part Number: 74LVC573
• Description: Octal D-type transparent latch with 5-volt tolerant inputs/outputs 3-State
• Manufacturer: PHILIPS [NXP Semiconductors]

1. C
2. The condition is V
Philips Semiconductors
FEATURES
DESCRIPTION
The 74LVC573A is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
QUICK REFERENCE DATA
NOTE:
ORDERING INFORMATION
t
C
C
20-Pin Plastic Shrink Small Outline (SO)
20-Pin Plastic Shrink Small Outline (SSOP) Type II
20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I
1998 Jul 29
PHL
5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
Supply voltage range of 2.7V to 3.6V
Complies with JEDEC standard no. 8-1A
Inputs accept voltages up to 5.5V
CMOS low power consumption
Direct interface with TTL levels
High impedance when V
Flow-through pin-out architecture
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
I
PD
P
f
f
S (C
i
o
PD
D
= input frequency in MHz; C
/t
= output frequency in MHz; V
PLH
= C
SYMBOL
L
is used to determine the dynamic power dissipation (P
x V
PD
CC
x V
2
CC
x f
2
o
) = sum of outputs.
x f
I
= GND to V
i
PACKAGES
+ S (C
Power dissipation capacitance per latch
Propagation delay
D
LE to Q
Input capacitance
CC
n
to Q
= 0V
L
x V
L
n;
n
CC
= output load capacity in pF;
CC
CC
= supply voltage in V;
2
PARAMETER
x f
o
) where:
TEMPERATURE
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
D
in mW):
RANGE
C
V
Notes 1 and 2
CC
L
2
= 50pF
= 3.3V
The 74LVC573A is an octal D-type transparent latch featuring
separate D-type inputs for each latch and 3-State outputs for
bus-oriented applications. A latch enable (LE) input and an output
enable (OE) input are common to all internal latches.
true outputs. When LE is HIGH, data at the D
latches. In this condition, the latches are transparent, i.e. a latch
output will change each time its corresponding D-input changes.
When LE is LOW, the latches store the information that was present
at the D-inputs one setup time preceding the HIGH-to-LOW
transition of LE. When OE is LOW, the contents of the eight latches
are available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
The ’573A’ is functionally identical to the ’373A’, but the ’373A’ has a
different pin arrangement.
The ’573A’ consists of eight D-type transparent latches with 3-State
CONDITIONS
NORTH AMERICA
74LVC573A PW
74LVC573A DB
74LVC573A D
OUTSIDE
NORTH AMERICA
7LVC573APW DH
74LVC573A DB
74LVC573A D
TYPICAL
4.3
4.6
5.0
20
74LVC573A
n
Product specification
inputs enters the
853-1862 19804
PKG. DWG. #
SOT163-1
SOT339-1
SOT360-1
UNIT
pF
pF
ns