AD7356_08 AD [Analog Devices], AD7356_08 Datasheet - Page 18

• Manufacturer Part Number: AD7356_08
• Description: Differential Input, Dual, Simultaneous Sampling, 5 MSPS, 12-Bit, SAR ADC
• Manufacturer: AD [Analog Devices]

AD7356
SERIAL INTERFACE
Figure 30 shows the detailed timing diagram for serial interfacing
to the AD7356. The serial clock provides the conversion clock
and controls the transfer of information from the AD7356
during conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track and hold into hold mode,
at which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires a minimum of 14 SCLKs to complete. Once
13 SCLK falling edges have elapsed, the track and hold goes
back into track on the next SCLK rising edge, as shown in
Figure 30
AD7356, then two trailing zeros appear after the final LSB.
On the rising edge of
SDATA
brought high, but is instead held low for an additional 14
SCLK cycles, the data from the conversion on ADC B is output
on SDATA
conversion on ADC A is output on SDATA
A
SDATA
and SDATA
at Point B. If a 16-bit data transfer is used on the
SDATA
SDATA
SCLK
A
SCLK
(see
CS
A
CS
THREE-
STATE
A
B
Figure 31
THREE-
STATE
B
CS , the conversion is terminated and
t
2
go back into three-state. If CS is not
2 LEADING
0
2 LEADING ZEROS
ZEROS
t
1
2
0
). Likewise, the data from the
t
3
0
1
t
3
0
2
DB11
2
A
DB11
Figure 31. Reading Data from Both ADCs on One SDATA Line with 32 SCLKs
3
DB10
B
A
. In this case, the
3
DB10
4
DB9
t
t
6
A
4
Figure 30. Serial Interface Timing Diagram
4
t
5
5
DB9
t
t
6
4
t
CONVERT
2 TRAILING ZEROS
5
t
14
7
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ZERO
DB8
t
7
15
ZERO
2 LEADING ZEROS
SDATA line in use goes back into three-state on the 32
falling edge or the rising edge of
A minimum of 14 serial clock cycles is required to perform
the conversion process and to access data from one conversion
on either data line of the AD7356. CS falling low provides the
leading zero to be read in by the microcontroller or DSP. The
remaining data is then clocked out by subsequent SCLK falling
edges, beginning with a second leading zero. Thus, the first
falling clock edge on the serial clock has the leading zero
provided and also clocks out the second leading zero. The
12-bit result then follows with the final bit in the data transfer
and is valid on the 14
the previous (13
SCLK, it may be possible to read in data on each SCLK rising
edge depending on the SCLK frequency. With a slower SCLK,
the first rising edge, of SCLK after the CS falling edge has the
second leading zero provided, and the 13
has DB0 provided.
16
ZERO
DB2
17
ZERO
t
5
DB1
DB11
th
) falling edge). In applications with a slower
13
B
B
t
DB0
8
th
falling edge (having been clocked out on
t
ACQUISITION
ZERO
THREE-STATE
2 TRAILING ZEROS
CS , whichever occurs first.
t
QUIET
ZERO
t
9
th
32
rising SCLK edge
t
10
THREE-
STATE
nd
SCLK