AD7366_07 AD [Analog Devices], AD7366_07 Datasheet - Page 19

• Manufacturer Part Number: AD7366_07
• Description: True Bipolar Input, Dual 1 ?s, 12-/14-Bit, 2-Channel SAR ADCs
• Manufacturer: AD [Analog Devices]

+10V/+5V
DRIVER AMPLIFIER CHOICE
The AD7366/AD7367 have a total of four analog inputs, which
operate in single-ended mode. Both ADC’s analog inputs can
be programmed to one of the three analog input ranges. In
applications where the signal source is high impedance, it is
recommended to buffer the signal before applying it to the
ADC analog inputs. Figure 21 shows the configuration of the
AD7366/AD7367 in single-ended mode.
In applications where the THD and SNR are critical specifi-
cations, the analog input of the AD7366/AD7367 should be
driven from a low impedance source. Large source impedances
significantly affect the ac performance of the ADC and can
necessitate the use of an input buffer amplifier.
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance depends on the amount of THD that can be tolerated
in the application. The THD increases as the source impedance
increases and performance degrades. Figure 7 shows THD vs.
the analog input frequency for various source impedances.
Depending on the input range and analog input configuration
selected, the AD7366/AD7367 can handle source impedances as
illustrated in Figure 7.
Due to the programmable nature of the analog inputs on the
AD7366/AD7367, the choice of op amp used to drive the
inputs is a function of the particular application and depends
on the analog input voltage ranges selected.
The driver amplifier must be able to settle for a full-scale step
to a 14-bit level, 0.0061%, in less than the specified acquisition
time of the AD7366/AD7367. An op amp such as the
meets this requirement when operating in single-ended mode.
The AD8021 needs an external compensating NPO type of
capacitor. The
applications where a dual version is required. For lower fre-
quency applications, recommended op amps are the AD797,
AD845, and AD8610.
–10V/–5V
AGND
Figure 21. Typical Connection Diagram with the AD8021 for Driving the
AD8022
*ADDITIONAL PINS OMITTED FOR CLARITY.
can also be used in high frequency
1kΩ
Analog Input
AD8021
+
15pF
1kΩ
V+
V–
0.1µF
0.1µF
10µF
10µF
C
COMP
V
A1
= 10pF
AD7367*
AD7366/
V
V
AD8021
DD
SS
+5V
V
CC
Rev. 0 | Page 19 of 28
V
The AD7366/AD7367 also have a V
voltage at which the serial interface operates. V
ADC to easily interface to both 3 V and 5 V processors. For
example, if the AD7366/AD7367 was operated with a V
5 V, the V
ing a large dynamic range with low voltage digital processors.
Thus, the AD7366/AD7367 could be used with the ±10 V input
range while still being able to interface to 3 V digital parts.
To achieve the maximum throughput rate of 1.12 MSPS for the
AD7366 or 1 MSPS for the AD7367, V
or equal to 4.75 V, see Table 2 and Table 3. The maximum
throughput rate with the V
and greater than 2.7 V is 1 MSPS for the AD7366 and 900 kSPS
for the AD7367.
REFERENCE
The AD7366/AD7367 can operate with either the internal 2.5 V
on-chip reference or an externally applied reference. The logic
state of the REFSEL pin determines whether the internal refer-
ence is used. The internal reference is selected for both ADC
when the REFSEL pin is tied to logic high. If the REFSEL pin is
tied to GND then an external reference can be supplied through
the D
be tied to either a low or high logic state for the part to operate.
Suitable reference sources for the AD7366/AD7367 include
AD780, AD1582, ADR431, REF193, and ADR391.
The internal reference circuitry consists of a 2.5 V band gap
reference and a reference buffer. When operating the AD7366/
AD7367 in internal reference mode, the 2.5 V internal reference
is available at the D
decoupled to AGND using a 680 nF capacitor. It is recom-
mended that the internal reference be buffered before applying
it elsewhere in the system. The internal reference is capable of
sourcing up to 150 μA with an analog input range of ±10 V
and 70 μA for both the ±5 V and 0 V to 10 V ranges.
If the internal reference operation is required for the ADC con-
version, the REFSEL pin must be tied to logic high on power-
up. The reference buffer requires 70 μs to power up and charge
the 680 nF decoupling capacitor during the power-up time.
The AD7366/AD7367 is specified for a 2.5 V to 3 V reference
range. When a 3 V reference is selected, the ranges are ±12 V,
±6 V, and 0 V to +12 V. For these ranges, the V
supply must be equal to or greater than the +12 V and −12 V
respectively.
DRIVE
CAP
A and D
DRIVE
pin could be powered from a 3 V supply, allow-
CAP
CAP
B pins. On power-up, the REFSEL pin must
A and D
DRIVE
CAP
voltage set to less than 4.75 V
B pins, which should be
DRIVE
AD7366/AD7367
DRIVE
feature to control the
must be greater than
DD
DRIVE
and V
allows the
CC
SS
of