AD9883/PCB AD [Analog Devices], AD9883/PCB Datasheet
AD9883/PCB
Related parts for AD9883/PCB
AD9883/PCB Summary of contents
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GENERAL DESCRIPTION The AD9883 is a complete 8-bit, 110 MSPS monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 110 MSPS encode rate capability and full-power analog bandwidth of 300 MHz supports resolutions ...
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AD9883–SPECIFICATIONS Analog Interface ( Parameter RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes ANALOG INPUT Input Voltage Range Minimum Maximum Gain Tempco Input Bias Current Input Offset Voltage Input Full-Scale Matching Offset ...
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Parameter POWER SUPPLY V Supply Voltage D V Supply Voltage DD P Supply Voltage VD I Supply Current ( Supply Current ( Supply Current ( Total Power Dissipation ...
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... Exposure to absolute maximum ratings for extended periods may affect device reliability. Model AD9883KST-110 AD9883/PCB CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9883 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges ...
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GND GREEN <7> GREEN <6> GREEN <5> GREEN <4> GREEN <3> GREEN <2> GREEN <1> GREEN <0> GND VDD BLUE <7> BLUE <6> BLUE <5> BLUE <4> BLUE <3> BLUE <2> BLUE <1> BLUE <0> GND CONNECT ...
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AD9883 PIN FUNCTION DETAIL Outputs HSOUT Horizontal Sync Output A reconstructed and phase-aligned version of the Hsync input. Both the polarity and dura- tion of this output can be programmed via serial bus registers. By maintaining alignment with DATACK, and ...
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CLAMP External Clamp Input This logic input may be used to define the time during which the input signal is clamped to ground. It should be exercised when the reference dc level is known to be present on the analog ...
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AD9883 At that point the signal should be resistively terminated (75 Ω to the signal ground return) and capacitively coupled to the AD9883 inputs through 47 nF capacitors. These capacitors form part of the dc restoration circuit ideal ...
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OFFSET = 7Fh 1.0 0.5 0.0 00h GAIN Gain and Offset Control The AD9883 can accommodate input signals with inputs rang- ing from 0 1.0 V full scale. The full-scale range is set in three 8-bit registers (Red ...
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AD9883 The PLL characteristics are determined by the loop filter design, by the PLL Charge Pump Current and by the VCO range setting. The loop filter design is illustrated in Figure 6. Recommended settings of VCO range and charge pump ...
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Table V. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats Standard Resolution 640 × 480 VGA 800 × 600 SVGA 1024 × 768 XGA 1280 × 1024 SXGA Timing The following timing diagrams show the operation ...
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AD9883 Coast Timing In most computer systems, the Hsync signal is provided con- tinuously on a dedicated wire. In these systems, the COAST input and function are unnecessary, and should not be used and the pin should be permanently connected ...
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Serial Register Map The AD9883 is initialized and controlled by a set of registers, which determine the operating modes. An external controller is employed to write and read the Control Registers through the 2-line serial interface port. Write and ...
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AD9883 Write and Hex Read or Default Address Read Only Bits Value 0FH R/W 7 10H R/W 7:3 10111 11H R/W 7:0 00100000 12H R/W 7:0 00000000 13H R/W 7:0 00000000 14H RO 7:0 15H 7:0 ...
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TWO-WIRE SERIAL CONTROL REGISTER DETAIL CHIP IDENTIFICATION 00 7–0 Chip Revision An 8-bit register which represents the silicon revision. Revision 0 = 0000 0000, Revision 1 = 0000 0001, Revision 2 = 0000 0010. PLL DIVIDER CONTROL 01 7–0 PLL ...
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AD9883 screen, and a slow recovery from large changes in the Average Picture Level (APL), or brightness. When Clamp Function = 1, this register is ignored. Hsync PULSEWIDTH 07 7–0 Hsync Output Pulsewidth An 8-bit register that sets the duration ...
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Active Hsync Select This bit is used under two conditions used to select the active Hsync when the override bit is set, (Bit 4). Alter- nately used to determine the active Hsync when not ...
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AD9883 0F 2 Seek Mode Override This bit is used to either allow or disallow the low-power mode. The low-power mode (seek mode) occurs when there are no signals on any of the Sync inputs. Table XXI. Seek Mode Override ...
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Table XXVII. Active Hsync Results Bit 7 Bit 1 Bit 4, Reg (Hsync (SOG 0EH Detect) Detect) (Override AHS = 0 means use the Hsync ...
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AD9883 2-WIRE SERIAL CONTROL PORT A 2-wire serial interface control interface is provided four AD9883 devices may be connected to the 2-wire serial interface, with each device having a unique address. The 2-wire serial interface comprises a clock ...
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Serial Interface Read/Write Examples Write to one control register ➥ Start Signal ➥ Slave Address Byte (R/W Bit = LOW) ➥ Base Address Byte ➥ Data Byte to Base Address ➥ Stop Signal Write to four consecutive control registers ➥ ...
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AD9883 Table XXXIV. Control of the Sync Block Muxes via the Serial Register Control Mux Serial Bus Bit Nos. Control Bit State Result 1 and 2 0EH: Bit 3 0 Pass Hsync 1 Pass Sync-on-Green 4 0EH: Bit 0 0 ...
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Some graphic controllers use substantially different levels of power when active (during active picture time) and when idle (during horizontal and vertical sync periods). This can result in a measurable change in the voltage supplied to the analog supply regulator, ...
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AD9883 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) COPLANARITY 0.004 (0.10) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 80-Lead LQFP (ST-80) 0.063 (1.60) 0.630 (16.00) BSC SQ MAX 0.551 (14.00) BSC SEATING PIN 1 PLANE TOP VIEW ...