ADC1210S065HN-C1 IDT [Integrated Device Technology], ADC1210S065HN-C1 Datasheet
ADC1210S065HN-C1
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ADC1210S065HN-C1 Summary of contents
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ADC1210S series Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs Rev. 03 — 2 July 2012 1. General description The ADC1210S is a single-channel 12-bit Analog-to-Digital Converter (ADC) optimized for ...
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... HVQFN40 plastic thermal enhanced very thin quad flat package; ADC1210S105HN-C1 105 HVQFN40 plastic thermal enhanced very thin quad flat package; ADC1210S080HN-C1 80 HVQFN40 plastic thermal enhanced very thin quad flat package; ADC1210S065HN-C1 65 HVQFN40 plastic thermal enhanced very thin quad flat package; 5. Block diagram ADC1210S INP INM Fig 1 ...
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Integrated Device Technology 6. Pinning information 6.1 Pinning terminal 1 index area REFB 1 REFT 2 AGND 3 VCM 4 5 VDDA ADC1210S HVQFN40 6 AGND INM 7 INP 8 AGND 9 VDDA 10 Transparent top view Fig 2. Pin ...
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Integrated Device Technology Table 2. Symbol D11 D10 n.c. n.c. DAV n.c. VDDO OGND OTR SCLK/DFS SDIO/ODS CS SENSE VREF [1] P: power supply; G: ground; I: input; O: output; ...
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Integrated Device Technology Table 3. Symbol n.c. DAVM DAVP [1] Pins and pins are the same for both CMOS and LVDS DDR outputs (see Table 2). [2] P: power supply; G: ground; I: input; ...
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Integrated Device Technology 9. Static characteristics [1] Table 6. Static characteristics Symbol Parameter Supplies V analog supply voltage DDA V output supply voltage DDO I analog supply current DDA I output supply current DDO P power dissipation Clock inputs: pins ...
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Integrated Device Technology [1] Table 6. Static characteristics Symbol Parameter Digital outputs, CMOS mode: pins D11 to D0, OTR, DAV Output levels DDO V LOW-level output voltage OL V HIGH-level output voltage OH C output capacitance ...
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Dynamic characteristics 10.1 Dynamic characteristics Table 7. Dynamic characteristics [1] Symbol Parameter Conditions Analog signal processing second harmonic MHz 2H i level MHz MHz 170 ...
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Table 7. Dynamic characteristics [1] …continued Symbol Parameter Conditions IMD Intermodulation MHz i distortion MHz MHz 170 MHz i [1] Typical values measured ...
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Table 8. Clock input and digital output timing characteristics Symbol Parameter Conditions LVDS DDR mode timing output: pins D10_D11_P to D0_D1_P, D10_D11_M to D0_D1_M, DAVP and DAVM t propagation DATA PD delay DAV t set-up time su t hold time ...
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Integrated Device Technology CLKP CLKM DATA DAV Fig 4. CMOS mode and clock timing Fig 5. LDVS DDR mode and clock timing ADC1210S_SER 3 Product data sheet Single 12-bit ADC; CMOS or LVDS DDR ...
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Integrated Device Technology 10.3 SPI timings Table 9. Symbol t w(SCLK) t w(SCLKH) t w(SCLKL clk(max) [1] Typical values measured at V values are across the full temperature range T Fig 6. SPI timing ADC1210S_SER ...
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Integrated Device Technology 10.4 Typical characteristics 3.2 C (pF) 3.0 2.8 2.6 2.4 50 150 250 350 Fig 7. Capacitance as a function of frequency 100 SFDR (dBc ...
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Integrated Device Technology 92 SFDR (dBc) (1) ( 40 C/typical supply voltages (1) T amb = +25 C/typical supply voltages (2) T amb = +90 C/typical supply voltages (3) T amb Fig ...
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Integrated Device Technology 11. Application information 11.1 Device control The ADC1210S can be controlled via SPI or directly via the I/O pins (Pin control mode). 11.1.1 SPI and Pin control modes The device enters Pin control mode at power-up, and ...
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Integrated Device Technology 11.1.4 Selecting the output data format The output data format can be selected via the SPI interface (offset binary, two’s complement or gray code; see Table 23 using pin DFS in Pin control mode (offset ...
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Integrated Device Technology Fig 17. Anti-kickback circuit The component values are determined by the input frequency and should be selected so as not to affect the input bandwidth. Table 11. Input frequency 3 MHz 70 MHz 170 MHz 11.2.3 Transformer ...
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Integrated Device Technology Fig 19. Dual transformer configuration suitable for a high intermediate frequency application 11.3 System reference and power management 11.3.1 Internal/external references The ADC1210S has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. ...
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Integrated Device Technology VREF SENSE Fig 20. Reference equivalent schematic If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or externally as detailed in Table 12. Table 12. Selection internal (Figure 21) internal (Figure ...
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Integrated Device Technology VREF 330 pF REFERENCE EQUIVALENT SCHEMATIC SENSE Fig 21. Internal reference (p-p) full-scale VREF 0.1 μF V REFERENCE EQUIVALENT SCHEMATIC SENSE VDDA Fig 23. External reference (p- (p-p) full-scale 11.3.2 ...
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Integrated Device Technology 11.3.3 Common-mode output voltage (V A 0.1 F filter capacitor should be connected between pin VCM and ground to ensure a low-noise common-mode output voltage. When AC-coupled, pin VCM can then be used to set the common-mode ...
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Integrated Device Technology a. Sine clock input c. LVPECL clock input Fig 27. Differential clock input 11.4.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in Figure 28. The common-mode voltage of the differential input ...
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Integrated Device Technology Single-ended or differential clock inputs can be selected via the SPI interface (see Table 21). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting ...
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Integrated Device Technology The output resistance is 50 and is the combination of an internal resistor and the equivalent output resistance of the buffer. There is no need for an external damping resistor. The drive strength of both data ...
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Integrated Device Technology Table 14. LVDS_INT_TER[2:0] 000 001 010 011 100 101 110 111 11.5.3 DAta Valid (DAV) output clock A data valid output clock signal (DAV) can be used to capture the data delivered by the ADC1210S. Detailed timing ...
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Integrated Device Technology 11.5.7 Output codes versus input voltage Table 16. INP INM < 1 1.0000000 0.9995117 0.9990234 0.9985352 0.9980469 .... 0.0009766 0.0004883 0.0000000 +0.0004883 +0.0009766 .... +0.9980469 +0.9985352 +0.9990234 +0.9995117 +1.0000000 > +1 11.6 Serial peripheral ...
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Integrated Device Technology Table 18 Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An ...
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Integrated Device Technology Fig 33. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR Fig 34. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS ADC1210S_SER 3 Product data sheet Single ...
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Register allocation map Table 19. Register allocation map Addr Register name R/W Hex Bit 7 0005 Reset and R/W SW_RST operating mode 0006 Clock R/W - 0008 Internal reference R/W - 0011 Output data R/W - standard 0012 Output ...
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Integrated Device Technology Table 20. Reset and operating mode control register (address 0005h) bit description Default values are highlighted. Bit Symbol Access 7 SW_RST R RESERVED[2: OP_MODE[1:0] R/W Table 21. ...
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Integrated Device Technology Table 22. Internal reference control register (address 0008h) bit description Default values are highlighted. Bit Symbol Access INTREF_EN R INTREF[2:0] R/W Table 23. Output data standard control register (address ...
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Integrated Device Technology Table 24. Output clock register (address 0012h) bit description Default values are highlighted. Bit Symbol Access DAVINV R DAVPHASE[2:0] R/W Table 25. Offset register (address 0013h) bit description Default ...
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Integrated Device Technology Table 27. Test pattern register 2 (address 0015h) bit description Default values are highlighted. Bit Symbol TESTPAT_USER[11:4] Table 28. Test pattern register 3 (address 0016h) bit description Default values are highlighted. Bit Symbol 7 ...
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Integrated Device Technology Table 31. LVDS DDR output register 1 (address 0021h) bit description Default values are highlighted. Bit Symbol Access DAVI_x2_EN R DAVI[1:0] R/W 2 DATAI_x2_EN R DATAI[1:0] ...
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Integrated Device Technology 12. Package outline HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 0.85 mm terminal 1 index area terminal 1 40 ...
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Integrated Device Technology 13. Revision history Table 33. Revision history Document ID Release date ADC1210S_SER v.3 20120702 ADC1210S_SER v.2 20101223 • Modifications: • • • ADC1210S_SER_1 20100409 14. Contact information For more information or sales office addresses, please visit: ADC1210S_SER ...
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Integrated Device Technology 15. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . ...