ADC1210S065HN-C1 IDT [Integrated Device Technology], ADC1210S065HN-C1 Datasheet - Page 28

no-image

ADC1210S065HN-C1

Manufacturer Part Number
ADC1210S065HN-C1
Description
Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs
Manufacturer
IDT [Integrated Device Technology]
Datasheet
Integrated Device Technology
ADC1210S_SER 3
Product data sheet
Fig 33. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR
Fig 34. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS
(CMOS LVDS DDR)
(CMOS LVDS DDR)
SDIO
SDIO
CS
CS
Rev. 03 — 2 July 2012
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
Offset binary, LVDS DDR
default mode at start-up
two's complement, CMOS
default mode at start-up
ADC1210S series
005aaa063
005aaa064
© IDT 2012. All rights reserved.
28 of 37

Related parts for ADC1210S065HN-C1