TLV320AIC3105_08 BURR-BROWN [Burr-Brown Corporation], TLV320AIC3105_08 Datasheet
TLV320AIC3105_08
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TLV320AIC3105_08 Summary of contents
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Burr Brown Products from Texas Instruments LOW-POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY FEATURES Stereo Audio DAC – 102-dBA Signal-to-Noise Ratio – 16/20/24/32-Bit Data – Supports Rates From 8 kHz to 96 kHz – 3D/Bass/Treble/EQ/De-Emphasis Effects – Flexible Power Saving ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS ...
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DINL DINR WCLK BCLK DOUTR DOUT DIN DOUTL SIMPLIFIED BLOCK DIAGRAM Submit Documentation Feedback TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 SDA SCL RESET MCLK MICBIAS DVSS IOVDD DVDD DRVSS DRVDD DRVDD AVSS_DAC AVDD_DAC AVSS_ADC 3 ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 PRODUCT PACKAGE TLV320AIC3105 QFN-32 DVDD RESET RIGHT_LOM RIGHT_LOP LEFT_LOM LEFT_LOP AVSS2 AVDD Connect device thermal pad to DRVSS. 4 PACKAGING/ORDERING INFORMATION PACKAGE OPERATING DESIGNATOR TEMPERATURE RANGE RHB – ...
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TERMINAL NAME QFN NO. AVDD 25 AVSS1 17 AVSS2 26 BCLK 2 DIN 4 DOUT 5 DRVDD 18 DRVDD 24 DRVSS 21 DVDD 32 DVSS 6 HPLCOM 20 HPLOUT 19 HPRCOM 22 HPROUT 23 IOVDD 7 LEFT_LOM 28 LEFT_LOP ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) AVDD to AVSS, DRVDD to DRVSS AVDD to DRVSS IOVDD to DVSS DVDD to DVSS AVDD to DRVDD Digital input ...
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ELECTRICAL CHARACTERISTICS AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1 PARAMETER AUDIO ADC Input signal level (0 dB) Single-ended input f (1) (2) Signal-to-noise ratio A-weighted f (1) (2) Dynamic range signal f ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 ELECTRICAL CHARACTERISTICS (continued AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1 PARAMETER MICROPHONE BIAS Bias voltage Current sourcing AUDIO DAC – Differential Line Output, Load ...
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ELECTRICAL CHARACTERISTICS (continued AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1 PARAMETER AUDIO DAC – Lineout and Headphone Out Drivers First option Second optiin Output common mode Third option Fourth option Output volume ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 ELECTRICAL CHARACTERISTICS (continued AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1 PARAMETER CURRENT CONSUMPTION – DRVDD, IOVDD = AVDD_DAC = 3.3 V, DVDD = 1.8 ...
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AUDIO DATA SERIAL INTERFACE TIMING DIAGRAMS All specifications at +25 C, DVDD = 1.8 V. WCLK BCLK SDOUT SDIN PARAMETER t (WS) ADWS/WCLK delay time d t (DO-WS) ADWS/WCLK to DOUT delay time d t (DO-BCLK) BCLK to DOUT ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 All specifications at +25 C, DVDD = 1.8 V. WCLK BCLK SDOUT SDIN PARAMETER t (WS) ADWS/WCLK delay time d t (DO-BCLK) BCLK to DOUT delay time d t (DI) DIN ...
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All specifications at +25 C, DVDD = 1.8 V. WCLK t (BCLK) H BCLK t (BCLK (BCLK) P SDOUT SDIN PARAMETER t (BCLK) BCLK high period H t (BCLK) BCLK low period L t (WS) ADWS/WCLK setup ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 All specifications at +25 C, DVDD = 1.8 V. WCLK t (BCLK) L BCLK t (BCLK (BCLK) P SDOUT SDIN PARAMETER t (BCLK) BCLK high period H t (BCLK) ...
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Load = 16 −10 AC-Coupled −20 −30 −40 −50 −60 −70 − −20 −40 −60 −80 −100 −120 −140 −160 TYPICAL CHARACTERISTICS HPL DRV = 2 HPL DRV = ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 TYPICAL CHARACTERISTICS (continued) 0 −20 −40 −60 −80 −100 −120 −140 −160 Input = −65 dBFS ...
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TYPICAL CHARACTERISTICS (continued) 0.85 0.8 0.75 0.7 0.65 0.6 0.55 0.5 0.45 0 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 2.7 2.8 2 PGA Setting (dB) Figure 9. ADC Gain Error ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 TYPICAL CHARACTERISTICS (continued) 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 −45 −35 −25 18 MICBIAS = AVDD MICBIAS = 2.5 V MICBIAS = 2 V −15 − ...
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TYPICAL CHARACTERISTICS (continued) TYPICAL CIRCUIT CONFIGURATION MICBIAS MIC1L/LINE1L A 0. MIC2L/LINE2L FM Tuner MIC2R/LINE2R 0. 0. LINE_L MIC3L/LINE3L/MICDET LINE_R 0. MIC3R/LINE3R ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 TYPICAL CHARACTERISTICS (continued) MICBIAS MIC1L/LINE1L A 0. MIC2L/LINE2L FM Tuner MIC2R/LINE2R 0. 0. LINE_L MIC3L/LINE3L/MICDET LINE_R 0. MIC3R/LINE3R ...
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The TLV320AIC3105 is a highly flexible, low-power, stereo audio codec with extensive feature integration, intended for applications in smartphones, PDAs, and portable computing, communication, and entertainment applications. Available in a 5-mm board space, and power consumption in space-constrained, battery-powered, ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 2 The I C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads from a slave, the slave drives the data line; ...
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In the case register write, if the master does not issue a STOP condition, then the device enters auto-increment mode the next eight clocks, the data on SDA is treated as data ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 WCLK BCLK SDIN/SDOUT 0 n–1 MSB Figure 16. Right-Justified Serial Data Bus Mode Operation LEFT-JUSTIFIED MODE In left-justified mode, the MSB of the right channel is valid on the rising edge ...
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WCLK BCLK 1 Clock Before MSB SDIN/SDOUT n–1 n–2 n–3 MSB Figure 18. I DSP MODE In DSP mode, the rising edge of the word clock starts the data transfer with the left-channel data first and immediately followed by ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Note that the location of the data when an offset is programmed is different, depending on what transfer mode is selected. In DSP mode, both left and right channels of data ...
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AUDIO CLOCK GENERATION The audio converters in the TLV320AIC3105 need an internal audio master clock at a frequency of 256 which can be obtained in a variety of manners from an external clock signal applied to the device. A ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Where CLKDIV_IN can be MCLK or BCLK, selected by register 102, bits D7–D6. NOTE – when NDAC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd ...
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S(ref) MCLK (MHz) P 2.048 1 3.072 1 4.096 1 6.144 1 8.192 19.2 1 19. STEREO AUDIO ADC The TLV320AIC3105 includes a ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 H(z) + 32, 768 * Programming the left channel is done by writing to page 1, registers 65–70, and the right channel is ...
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The AGC algorithm has several programmable settings, including target gain, attack and decay time constants, noise threshold, and maximum PGA gain applicable that allow the algorithm ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Input Signal Output Signal AGC Gain Figure 23. Typical Operation of the AGC Algorithm During Speech Recording Note that the time constants here are correct when the ADC is not in ...
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DIGITAL AUDIO PROCESSING FOR PLAYBACK The DAC channel consists of optional filters for de-emphasis and bass, treble, midrange level adjustment, speaker equalization, and 3-D effects processing. The de-emphasis function is implemented by a programmable digital filter block with fully ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Table 4. Default Digital Effects Processing Filter Coefficients, When in Independent Channel Processing Configuration 27619 The digital processing also includes capability to implement 3-D processing algorithms by providing ...
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DELTA-SIGMA AUDIO DAC The stereo audio DAC incorporates a third-order multibit delta-sigma modulator followed by an analog reconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and noise shaping techniques. The analog reconstruction filter design consists of a ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 CM SETTING 1.35 1.5 1.65 V 1.8 V AUDIO DAC POWER CONTROL The stereo DAC can be fully powered up or down, and in addition, the analog circuitry in each DAC ...
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Gain = 0, –1.5, – –12 dB, Mute MIC1L/LINE1L Gain = 0, –1.5, – –12 dB, Mute MIC2L/LINE2L Gain = 0, –1.5, – –12 dB, Mute MIC1R/LINE1R Gain = 0, ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY In addition to the input bypass path described above, the TLV320AIC3105 also includes the ability to route the ADC PGA output signals past the ADC, ...
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LINE2L MIC2L/LINE2L LINE1L MIC1L/LINE1L LINE1R MIC1R/LINE1R LINE2R MIC2R/LINE2R Figure 27. Passive Analog Bypass Mode Configuration SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 LINE2L LINE1L LINE2R LINE1R Submit Documentation Feedback TLV320AIC3105 SW-L2 SW-L1 SW-L0 LEFT_LOP LEFT_LOM SW-R2 SW-R1 SW-R0 ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS The TLV320AIC3105 has two fully differential line output drivers, each capable of driving a 10-k load. The output stage design leading to the fully differential ...
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MIC2L/LINE2L MIC2R/LINE2R PGA_L PGA_R DAC_L1 DAC_R1 Figure 29. Detail of the Volume Control and Mixing Function Shown in The DAC_L/R signals are the outputs of the stereo audio DAC, which can be steered by register control based on the ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 The output stage architecture leading to the high-power output drivers is shown in control and mixing blocks being effectively identical to that shown in have a output level control block like ...
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The high-power output drivers include additional circuitry to avoid artifacts on the audio output during power-on and power-off transient conditions. The user should first program the type of output configuration being used in page 0, register 14 to allow ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Stereo Cellular Stereo + Cellular m = mic s = ear speaker g = ground/vcm Figure 31. Configuration of Device for ...
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Differential Headphone Connector Assembly Figure 33. Configuration of Device for Jack Detection Using a Fully Differential Stereo Headphone CONTROL REGISTERS The control registers for the TLV320AIC3105 are described in detail below. All registers are 8 bits in width, with ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Page 0/Register 2: Codec Sample Rate Select Register BIT READ/ RESET WRITE VALUE D7–D4 R/W 0000 ADC Sample Rate Select 0000: ADC f 0001: ADC f 0010: ADC f 0011: ADC ...
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Page 0/Register 3: PLL Programming Register A BIT READ/ RESET WRITE VALUE D7 R/W 0 PLL Control Bit 0: PLL is disabled 1: PLL is enabled D6–D3 R/W 0010 PLL Q Value 0000 0001 ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Page 0/Register 4: PLL Programming Register B BIT READ/ RESET WRITE VALUE D7–D2 R/W 0000 01 PLL J Value 0000 00: Reserved; do not write this sequence. 0000 01 ...
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Page 0/Register 8: Audio Serial Data Interface Control Register A BIT READ/ RESET WRITE VALUE D7 R/W 0 Bit Clock Directional Control 0: BCLK is an input (slave mode) 1: BCLK is an output (master mode) D6 R/W 0 ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Page 0/Register 10: Audio Serial Data Interface Control Register C BIT READ/ RESET WRITE VALUE D7–D0 R/W 0000 0000 Audio Serial Data Word Offset Control This register determines where valid data ...
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Page 0/Register 12: Audio Codec Digital Filter Control Register BIT READ/ RESET WRITE VALUE D7–D6 R/W 00 Left-ADC High-Pass Filter Control 00: Left-ADC high-pass filter disabled 01: Left-ADC high-pass filter –3-dB frequency = 0.0045 10: Left-ADC high-pass filter –3-dB ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Page 0/Register 14: Headset/Button Press Detection Register B BIT READ/ RESET WRITE VALUE D7 R/W 0 Driver Capacitive Coupling 0: Programs high-power outputs for capless driver configuration 1: Programs high-power outputs ...
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Page 0/Register 17: MIC3L/R to Left-ADC Control Register BIT READ/ RESET WRITE VALUE D7–D4 R/W 1111 MIC3L Input Level Control for Left-ADC PGA Mix Setting the input level control to a gain below automatically connects MIC3L to the left-ADC ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Page 0/Register 19: LINE1L to Left-ADC Control Register BIT READ/ RESET WRITE VALUE D7 R/W 0 Reserved D6–D3 R/W 1111 LINE1L Input Level Control for Left-ADC PGA Mix Setting the input ...
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Page 0/Register 21: LINE1R to Left-ADC Control Register BIT READ/ RESET WRITE VALUE D7 R/W 0 Reserved D6–D3 R/W 1111 LINE1R Input Level Control for Left-ADC PGA Mix Setting the input level control to a gain below automatically connects ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Page 0/Register 23: LINE2R to Right ADC Control Register BIT READ/ RESET WRITE VALUE D7 R/W 0 Reserved D6–D3 R/W 1111 LINE2R Input Level Control for Right ADC PGA Mix Setting ...
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Page 0/Register 26: Left-AGC Control Register A BIT READ/ RESET WRITE VALUE D7 R/W 0 Left-AGC Enable 0: Left AGC is disabled. 1: Left AGC is enabled. D6–D4 R/W 000 Left-AGC Target Level 000: Left-AGC target level = –5.5 ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Page 0/Register 29: Right AGC Control Register A BIT READ/ RESET WRITE VALUE D7 R/W 0 Right AGC Enable 0: Right AGC is disabled 1: Right AGC is enabled D6–D4 R/W ...
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Page 0/Register 32: Left-AGC Gain Register BIT READ/ RESET WRITE VALUE D7–D0 R 0000 0000 Left-Channel Gain Applied by AGC Algorithm 1110 1000: Gain = –12.0-dB 1110 1001: Gain = –11.5-dB 1110 1010: Gain = –11.0-dB 0000 0000: Gain ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Page 0/Register 35: Right AGC Noise Gate Debounce Register BIT READ/ RESET WRITE VALUE D7–D3 R/W 0000 0 Right AGC Noise Detection Debounce Control These times 0000 0: Debounce = 0 ...
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Page 0/Register 37: DAC Power and Output Driver Control Register BIT READ/ RESET WRITE VALUE D7 R/W 0 Left-DAC Power Control 0: Left DAC is not powered up. 1: Left DAC is powered up. D6 R/W 0 Right DAC ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Page 0/Register 40: High-Power Output Stage Control Register BIT READ/ RESET WRITE VALUE D7–D6 R/W 00 Output Common-Mode Voltage Control 00: Output common-mode voltage = 1.35 V 01: Output common-mode voltage ...
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Page 0/Register 42: Output Driver Pop Reduction Register BIT READ/ RESET WRITE VALUE D7–D4 R/W 0000 Output Driver Power-On Delay Control 0000: Driver power-on time = 0 μs 0001: Driver power-on time = 10 μs 0010: Driver power-on time ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Output Stage Volume Controls A basic analog volume control with range from –78 dB and mute is replicated multiple times in the output stage network, connected to each ...
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Page 0/Register 46: PGA_L to HPLOUT Volume Control Register BIT READ/ RESET WRITE VALUE D7 R/W 0 PGA_L Output Routing Control 0: PGA_L is not routed to HPLOUT 1: PGA_L is routed to HPLOUT D6–D0 R/W 000 0000 PGA_L ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Page 0/Register 51: HPLOUT Output Level Control Register BIT READ/ RESET WRITE VALUE D7–D4 R/W 0000 HPLOUT Output Level Control 0000: Output level control = 0 dB 0001: Output level control ...
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Page 0/Register 55: LINE2R to HPLCOM Volume Control Register BIT READ/ RESET WRITE VALUE D7 R/W 0 LINE2R Output Routing Control 0: LINE2R is not routed to HPLCOM 1: LINE2R is routed to HPLCOM D6–D0 R/W 000 0000 LINE2R ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Page 0/Register 59: LINE2L to HPROUT Volume Control Register BIT READ/ RESET WRITE VALUE D7 R/W 0 LINE2L Output Routing Control 0: LINE2L is not routed to HPROUT 1: LINE2L is ...
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Page 0/Register 65: HPROUT Output Level Control Register BIT READ/ RESET WRITE VALUE D7–D4 R/W 0000 HPROUT Output Level Control 0000: Output level control = 0 dB 0001: Output level control = 1 dB 0010: Output level control = ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Page 0/Register 69: LINE2R to HPRCOM Volume Control Register BIT READ/ RESET WRITE VALUE D7 R/W 0 LINE2R Output Routing Control 0: LINE2R is not routed to HPRCOM 1: LINE2R is ...
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Page 0/Register 80: LINE2L to LEFT_LOP/M Volume Control Register BIT READ/ RESET WRITE VALUE D7 R/W 0 LINE2L Output Routing Control 0: LINE2L is not routed to LEFT_LOP/M 1: LINE2L is routed to LEFT_LOP/M D6–D0 R/W 000 0000 LINE2L ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Page 0/Register 86: LEFT_LOP/M Output Level Control Register BIT READ/ RESET WRITE VALUE D7–D4 R/W 0000 LEFT_LOP/M Output Level Control 0000: Output level control = 0 dB 0001: Output level control ...
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Page 0/Register 91: PGA_R to RIGHT_LOP/M Volume Control Register BIT READ/ RESET WRITE VALUE D7 R/W 0 PGA_R Output Routing Control 0: PGA_R is not routed to RIGHT_LOP/M 1: PGA_R is routed to RIGHT_LOP/M D6–D0 R/W 000 0000 PGA_R ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Page 0/Register 94: Module Power Status Register BIT READ/ RESET WRITE VALUE Left-DAC Power Status 0: Left DAC is not fully powered up. 1: Left DAC is fully ...
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Page 0/Register 96: Sticky Interrupt Flags Register BIT READ/ RESET WRITE VALUE HPLOUT Short-Circuit Detection Status 0: No short circuit detected at HPLOUT driver 1: Short circuit detected at HPLOUT driver HPROUT Short-Circuit ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Table 9.36. Page 0/Register 101: Clock Register BIT READ/ RESET WRITE VALUE D7–D1 R 0000 000 Reserved. Write only zeros to these bits. D0 R/W 0 CODEC_CLKIN Source Selection 0: CODEC_CLKIN ...
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Page 0/Register 104: Left AGC New Programmable Decay Time Register BIT READ/ RESET WRITE VALUE D7 R/W 0 Decay Time Register Selection 0: Decay time for the Left AGC is generated from register 26. 1: Decay time for the ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Page 0/Register 106: Right AGC New Programmable Decay Time Register BIT READ/ RESET WRITE VALUE D7 R/W 0 Decay Time Register Selection 0: Decay time for the right AGC is generated ...
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Page 0/Register 108: Passive Analog Signal Bypass Selection During Power Down Register BIT READ/ RESET WRITE VALUE D7 R/W 0 Reserved. Only write this bit. D6 R/W 0 LINE2RP Path Selection 0: Normal Signal Path 1: ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Page 1/Register 1: Left Channel Audio Effects Filter N0 Coefficient MSB Register BIT READ/ RESET WRITE VALUE D7–D0 R/W 0110 1011 Left-Channel Audio Effects Filter N0 Coefficient MSB The 16-bit integer ...
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Page 1/Register 8: Left Channel Audio Effects Filter N3 Coefficient LSB Register BIT READ/ RESET WRITE VALUE D7–D0 R/W 1110 0011 Left Channel Audio Effects Filter N3 Coefficient LSB The 16-bit integer contained in the MSB and LSB registers ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Page 1/Register 16: Left Channel Audio Effects Filter D2 Coefficient LSB Register BIT READ/ RESET WRITE VALUE D7–D0 R/W 1110 1110 Left Channel Audio Effects Filter D2 Coefficient LSB The 16-bit ...
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Page 1/Register 24: Left Channel De-Emphasis Filter N1 Coefficient LSB Register BIT READ/ RESET WRITE VALUE D7–D0 R/W 0010 1101 Left Channel De-Emphasis Filter N1 Coefficient LSB. The 16-bit integer contained in the MSB and LSB registers for this ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Page 1/Register 32: Right Channel Audio Effects Filter N2 Coefficient LSB Register BIT READ/ RESET WRITE VALUE D7–D0 R/W 0101 1101 Right Channel Audio Effects Filter N2 Coefficient LSB The 16-bit ...
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Page 1/Register 40: Right Channel Audio Effects Filter D1 Coefficient LSB Register BIT READ/ RESET WRITE VALUE D7–D0 R/W 1000 0011 Right Channel Audio Effects Filter D1 Coefficient LSB The 16-bit integer contained in the MSB and LSB registers ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Page 1/Register 48: Right Channel De-Emphasis Filter N0 Coefficient LSB Register BIT READ/ RESET WRITE VALUE D7–D0 R/W 0101 0101 Right Channel De-Emphasis Filter N0 Coefficient LSB. The 16-bit integer contained ...
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Page 1/Register 65: Left Channel ADC High-Pass Filter N0 Coefficient MSB Register BIT READ/ RESET WRITE VALUE D7–D0 R/W 0011 1001 Left Channel ADC High-Pass Filter N0 Coefficient MSB. The 16-bit integer contained in the MSB and LSB registers ...
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TLV320AIC3105 SLAS513A – FEBRUARY 2007 – REVISED JULY 2007 Page 1/Register 73: Right Channel ADC High-Pass Filter N1 Coefficient MSB Register BIT READ/ RESET WRITE VALUE D7–D0 R/W 1111 0011 Right Channel ADC High-Pass Filter N1 Coefficient MSB. The 16-bit ...
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PACKAGING INFORMATION (1) Orderable Device Status TLV320AIC3105IRHBR ACTIVE TLV320AIC3105IRHBT ACTIVE TLVAIC3105IRHBRG4 ACTIVE TLVAIC3105IRHBTG4 ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be ...
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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing TLV320AIC3105IRHBR QFN RHB PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 (mm) Diameter Width (mm) W1 (mm) 32 3000 330.0 12.4 5.3 Pack Materials-Page 1 19-Mar-2008 ...
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Device Package Type TLV320AIC3105IRHBR QFN PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) RHB 32 3000 Pack Materials-Page 2 19-Mar-2008 Width (mm) Height (mm) 340.5 333.0 20.6 ...
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Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the ...