AD8421 AD [Analog Devices], AD8421 Datasheet - Page 20

• Manufacturer Part Number: AD8421
• Description: 3 nV/?Hz, Low Power
• Manufacturer: AD [Analog Devices]

AD8421
THEORY OF OPERATION
ARCHITECTURE
The
topology has two stages: a preamplifier to provide differential
amplification, followed by a difference amplifier that removes the
common-mode voltage. Figure 61 shows a simplified schematic
of the AD8421.
Topologically, Q1, A1, R1 and Q2, A2, R2 can be viewed as
precision current feedback amplifiers. Input Transistors Q1 and
Q2 are biased at a fixed current so that any input signal forces
the output voltages of A1 and A2 to change accordingly. The
differential signal applied to the inputs is replicated across the
R
creating a gained differential voltage between Node 1 and Node 2.
The amplified differential and common-mode signals are applied
to a difference amplifier that rejects the common-mode voltage
but preserves the amplified differential voltage. The difference
amplifier employs innovations that result in very low output errors
such as offset voltage and drift, distortion at various loads, as well
as output noise. Laser-trimmed resistors allow for a highly accurate
in-amp with gain error less than 0.01% and CMRR that exceeds
94 dB (G = 1). The high performance pinout and special attention
given to design and layout allow for high CMRR performance
across a wide frequency and temperature range.
Using superbeta input transistors and bias current compensation,
the
rent, low offset current, low current noise, and extremely low
voltage noise of 3 nV/√Hz. The current-limiting and overvoltage
protection scheme allow the input to go 40 V from the opposite
rail at all gains without compromising the noise performance.
The transfer function of the
where G = 1 +
G
pins. Any current through R
AD8421
AD8421
V
OUT
= G × (V
–IN
offers extremely high input impedance, low bias cur-
is based on the classic 3-op-amp topology. This
9
9 .
R
OVERVOLTAGE
COMPENSATION
PROTECTION
G
kΩ
+IN
ESD AND
− V
−IN
) + V
AD8421
I
B
G
also flows through R1 and R2,
REF
I
superβ
Q1
I
is
NODE 3
4.95kΩ
C1
R1
+V
A1
S
NODE 1
+V
S
GAIN STAGE
–V
R
G
S
Figure 61. Simplified Schematic
V
B
+V
Rev. 0 | Page 20 of 28
S
A2
NODE 2
R2
4.95kΩ
NODE 4
C2
superβ
Q2
Users can easily and accurately set the gain using a single
standard resistor.
GAIN SELECTION
Placing a resistor across the R
AD8421. The gain can be calculated by referring to Table 6 or
by using the following gain equation:
The
determine the total gain accuracy of the system, add the tolerance
and gain drift of the R
When the gain resistor is not used, gain error and gain drift are
minimal.
Table 6. Gains Achieved Using 1% Resistors
1% Standard Table Value of R
10 kΩ
2.49 kΩ
1.1 kΩ
523 Ω
200 Ω
100 Ω
49.9 Ω
20 Ω
10 Ω
4.99 Ω
R
The
onto the R
to handle the expected power dissipation at ambient temperature.
G
I
I
Power Dissipation
AD8421
AD8421
R
I
COMPENSATION
B
G
OVERVOLTAGE
=
PROTECTION
ESD AND
9
G
G
9 .
resistor. Choose an R
defaults to G = 1 when no gain resistor is used. To
−
kΩ
duplicates the differential voltage across its inputs
1
G
10kΩ
10kΩ
resistor to the specifications of the AD8421.
+IN
AMPLIFIER STAGE
DIFFERENCE
10kΩ
G
10kΩ
G
A3
terminals sets the gain of the
G
+V
–V
resistor size that is sufficient
S
S
+V
–V
S
S
Calculated Gain
1.99
4.98
10.00
19.93
50.50
100.0
199.4
496.0
991.0
1985
OUTPUT
REF
Data Sheet