AD5426YRM-REEL7 AD [Analog Devices], AD5426YRM-REEL7 Datasheet - Page 16

• Manufacturer Part Number: AD5426YRM-REEL7
• Description: 8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface
• Manufacturer: AD [Analog Devices]

AD5426/AD5432/AD5443
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Since only a fraction D of the current into the V
routed to the I
as follows:
where R is the DAC resistance at the V
leakage current of 10 nA, R = 10 kΩ and a gain (i.e., 1/D) of 16
the error voltage is 1.6 mV.
REFERENCE SELECTION
When selecting a reference for use with the AD5426 series of
current output DACs, pay attention to the references output
voltage temperature coefficient specification. This parameter not
only affects the full-scale error, but can also affect the linearity
(INL and DNL) performance. The reference temperature coeffi-
cient should be consistent with the system accuracy specifications.
For example, an 8-bit system required to hold its overall specifi-
cation to within 1 LSB over the temperature range 0°C to 50°C
dictates that the maximum system drift with temperature should be
less than 78 ppm/°C. A 12-bit system with the same temperature
range to overall specification within 2 LSBs requires a maximum
drift of 10 ppm/°C. By choosing a precision reference with low
output temperature coefficient, this error source can be minimized.
Table IV suggests some references available from Analog Devices
that are suitable for use with this range of current output DACs.
Part No.
ADR01
ADR02
ADR03
ADR425
Part No.
OP97
OP1177
AD8551
Part No.
AD8065
AD8021
AD8038
AD9631
Output Error Voltage Due to DAC Leakage = (Leakage
Table VI. Listing of Some High Speed ADI Op Amps Suitable for Use with AD5426/AD5432/AD5443 DACs
Table IV. Suitable ADI Precision References Recommended for Use with AD5426/AD5432/AD5443 DACs
OUT
Output Voltage
10 V
5 V
2.5 V
5 V
Max Supply Voltage (V)
± 20
± 18
+6
1 terminal, the output voltage has to change
Table V. Some Precision ADI Op Amps Suitable for Use with AD5426/AD5432/AD5443 DACs
Max Supply Voltage
(V)
± 12
± 12
± 5
± 5
Initial Tolerance
0.1%
0.1%
0.2%
0.04%
REF
terminal. For a DAC
REF
V
25
60
5
OS
terminal is
BW @ A
(MHz)
145
200
350
320
(max) ( V)
R)/D
Temperature Drift
3 ppm/°C
3 ppm/°C
3 ppm/°C
3 ppm/°C
CL
–16–
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset volt-
age. The input offset voltage of an op amp is multiplied by the
variable gain (due to the code dependent output resistance of
the DAC) of the circuit. A change in this noise gain between
two adjacent digital fractions produces a step change in the
output voltage due to the amplifier’s input offset voltage. This
output voltage change is superimposed on the desired change in
output between the two codes and gives rise to a differential
linearity error, which, if large enough, could cause the DAC to
be nonmonotonic. In general, the input offset voltage should be
a fraction (~ <1/4) of an LSB to ensure monotonic behavior
when stepping through codes.
The input bias current of an op amp also generates an offset at
the voltage output as a result of the bias current flowing in the
feedback resistor R
enough to prevent any significant errors in 12-bit applications.
Common-mode rejection of the op amp is important in voltage
switching circuits since it produces a code dependent error at
the voltage output of the circuit. Most op amps have adequate
common-mode rejection for use at 8-, 10-, and 12-bit resolution.
Provided the DAC switches are driven from true wideband low
impedance sources (V
quently, the slew rate and settling time of a voltage switching DAC
circuit is determined largely by the output op amp. To obtain
minimum settling time in this configuration, it is important to
minimize capacitance at the V
this application) of the DAC. This is done by using low inputs
capacitance buffer amplifiers and careful board design.
I
0.1
2
0.05
B
Slew Rate
(V/ s)
180
100
425
1300
(max) (nA)
0.1 Hz to 10 Hz Noise
20 V p-p
10 V p-p
10 V p-p
3.4 V p-p
FB
. Most op amps have input bias currents low
GBP (MHz)
0.9
1.3
1.5
IN
V
( V)
1500
1000
3000
10000
OS
and AGND), they settle quickly. Conse-
(max)
REF
node (voltage output node in
Slew Rate (V/ s)
0.2
0.7
0.4
Package
SC70, TSOT, SOIC
SC70, TSOT, SOIC
SC70, TSOT, SOIC
MSOP, SOIC
I
(nA)
0.01
1000
0.75
7000
B
(max)
REV. 0