DAC7715UB1K BURR-BROWN [Burr-Brown Corporation], DAC7715UB1K Datasheet - Page 14

• Manufacturer Part Number: DAC7715UB1K
• Description: Quad, Serial Input, 12-Bit, Voltage Output DIGITAL-TO-ANALOG CONVERTER
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

TABLE II. Control Logic Truth Table.
TABLE III. Serial Shift Register Truth Table.
“load all DAC registers” signal (LOADDACS). In addition,
a chip select (CS) input is available to enable serial commu-
nication when there are multiple serial devices. An asyn-
chronous reset input (RESET) is provided to simplify start-
up conditions, periodic resets, or emergency resets to a
known state.
The DAC code and address are provided via a 16-bit serial
interface as shown in Figure 4. The first two bits select the
input register that will be updated when LOADREG goes
LOW, as shown in Table II. The next two bits are not used.
The last 12 bits are the DAC code which is provided, most
significant bit first.
Note that CS and CLK are combined with an OR gate and
the output controls the serial-to-parallel shift register inter-
nal to the DAC7715 (see the block diagram on the front of
this data sheet). These two inputs are completely inter-
changeable. In addition, care must be taken with the state of
NOTES: (1) L = Logic LOW. (2) H = Logic HIGH. (3) X = Don’t Care. (4) Resets to either 000H or 800
When RESET rises, all registers that are in their latched state retain the reset value.
NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH.
(3) X = Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition.
(6) A HIGH value is suggested in order to avoid a “false clock” from
advancing the shift register and changing the shift register. (7) If data is
clocked into the serial register while LOADREG is LOW, the selected input
register will change as the shift register bits “flow” through A1 and A0. This
will corrupt the data in each input register that has been erroneously
selected. (8) RESET LOW causes no change in the contents of the serial
shift register.
CS
H
H
H
L
L
(2)
(4)
(6)
(6)
(1)
X
L
A1
H
H
X
X
L
(1)
(3)
CLK
X
X
X
L
L
(3)
(5)
(1)
®
DAC7715
LOADREG
A0
H
H
L
L
X
X
X
L
H
H
H
H
H
(7)
RESET
LOADREG
L
H
H
H
H
H
(8)
H
H
X
L
L
L
L
SERIAL SHIFT REGISTER
Advanced One Bit
Advanced One Bit
LOADDACS
No Change
No Change
No Change
No Change
H
H
H
H
H
X
L
(2)
RESET
H
H
H
H
H
H
L
14
CLK when CS rises at the end of a serial transfer. If CLK is
LOW when CS rises, the OR gate will provide a rising edge
to the shift register, shifting the internal data one additional
bit. The result will be incorrect data and possible selection of
the wrong input register.
If both CS and CLK are used, then CS should rise only when
CLK is HIGH. If not, then either CS or CLK can be used to
operate the shift register. See Table III for more information.
The digital data into the DAC7715 is double-buffered. This
allows new data to be entered for each DAC without disturb-
ing the analog outputs. When the new settings have been
entered into the device, all of the DAC outputs can be
updated simultaneously. The transfer from the input regis-
ters to the DAC registers is accomplished with a HIGH to
LOW transition on the LOADDACS input.
Because the DAC registers become transparent when
LOADDACS is LOW, it is possible to keep this pin LOW
and update each DAC via LOADREG. However, as each
new data word is entered into the device, the corresponding
output will update immediately when LOADREG is taken
LOW.
Digital Input Coding
The DAC7715 input data is in Straight Binary format. The
output voltage is given by the following equation:
where N is the digital input code (in decimal). This equation
does not include the effects of offset (zero-scale) or gain
(full-scale) errors.
SELECTED
REGISTER
INPUT
NONE
NONE
ALL
A
B
C
D
V
OUT
H
, per the RESETSEL state (LOW = 000
V
REFL
(All Latched)
(All Latched)
SELECTED
Transparent
Transparent
Transparent
Transparent
REGISTER
STATE OF
Reset
INPUT
(
V
REFH
(4)
–
4096
V
REFL
) •
REGISTERS
Transparent
STATE OF
ALL DAC
H
Latched
Latched
Latched
Latched
Latched
Reset
, HIGH = 800
N
(4)
H
).