ADSP-BF538 AD [Analog Devices], ADSP-BF538 Datasheet
ADSP-BF538
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ADSP-BF538 Summary of contents
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... SRAM/cache 64K bytes of instruction SRAM 32K bytes of data SRAM 32K bytes of data SRAM/cache 4K bytes of scratchpad SRAM 512K bytes or 1M byte of flash memory (ADSP-BF538F parts only) Four dual-channel memory DMA controllers TWI0-1 CAN 2.0B GPIO PORT ...
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... ADSP-BF538/ADSP-BF538F TABLE OF CONTENTS General Description ................................................. 3 Low Power Architecture ......................................... 3 System Integration ................................................ 3 ADSP-BF538/ADSP-BF538F Processor Peripherals ....... 3 Blackfin Processor Core .......................................... 4 Memory Architecture ............................................ 5 DMA Controllers .................................................. 8 Real Time Clock ................................................... 9 Watchdog Timer .................................................. 9 Timers ............................................................... 9 Serial Ports (SPORTs) .......................................... 10 Serial Peripheral Interface (SPI) Ports ...................... 10 Two Wire Interface ............................................. 10 UART Ports ...................................................... 10 General-Purpose Ports ......................................... 11 Parallel Peripheral Interface ...
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... The ADSP-BF538/ADSP-BF538F processors include an on-chip voltage regulator in support of the ADSP-BF538/ADSP-BF538F processor’s dynamic power management capability. The voltage regulator provides a range of core voltage levels from a single 2. 3.6 V input. The voltage regulator can be bypassed at the user's discretion ...
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... ADSP-BF538/ADSP-BF538F BLACKFIN PROCESSOR CORE As shown in Figure 2 on Page 4, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu- tation units process 8-bit, 16-bit, or 32-bit data from the register file. ...
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... C/C++ compiler, resulting in fast and efficient software implementations. MEMORY ARCHITECTURE The ADSP-BF538/ADSP-BF538F processors view memory as a single unified 4 Gbyte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space ...
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... Figure 4. Internal Connection of Flash Memory (ADSP-BF538Fx) The ADSP-BF538F4 contains a 512 Kbits bottom boot sector flash memory. The ADSP-BF538F8 contains a 1 Mbit bottom boot sector flash memory. Features include the following. • access times as fast (EBIU registers must be set appropriately) • ...
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... The system interrupt controllers (SIC0, SIC1) provide the map- ping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the ADSP-BF538/ADSP-BF538F processors provide a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment registers (IAR) ...
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... MDMA1 Stream 0 Interrupt MDMA1 Stream 1 Interrupt Software Watchdog Timer Event Control The ADSP-BF538/ADSP-BF538F processors provide the user with a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each register is 16 bits wide: • CEC interrupt latch register (ILAT) – The ILAT register indicates when events have been latched ...
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... Like the other peripherals, the RTC can wake up the ADSP- BF538/ADSP-BF538F processor from sleep mode upon genera- tion of any RTC wakeup event. Additionally, an RTC wakeup event can wake up the processor from deep sleep mode, and wake up the on-chip internal voltage regulator from a powered down state ...
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... SCLK pling of data on the two serial data lines. TWO WIRE INTERFACE The ADSP-BF538/ADSP-BF538F processors have 2 two wire interface (TWI) modules that are compatible with the Philips Inter-IC bus standard. The TWI modules offer the capabilities of simultaneous master and slave operation, support for 7-bit addressing and multimedia data arbitration ...
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... The capabilities of the UARTs are further extended with sup- port for the Infrared Data Association (IrDA Physical Layer Link Specification (SIR) protocol. GENERAL-PURPOSE PORTS The ADSP-BF538/ADSP-BF538F processors have gen- eral-purpose I/O pins that are multiplexed with other peripherals. They are arranged into ports and F as shown in Table 4 ...
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... PPI_CONTROL register. Frame Capture Mode Frame capture mode allows the video source(s) to act as a slave (e.g., for frame capture). The ADSP-BF538/ADSP-BF538F pro- cessors control when to read from the video source(s). PPI_FS1 is an HSYNC output and PPI_FS2 is a VSYNC output. Output Mode Output mode is used for transmitting video or other data with up to three output frame syncs ...
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... CCLKRED • V Rev. PrD | Page May 2006 ADSP-BF538/ADSP-BF538F ) provide the lowest static power dissipation. DDINT is still supplied in this mode, all of the DDEXT Table 6, the ADSP-BF538/ADSP-BF538F proces- DDINT ) to be dynamically controlled. CCLK Power Savings Factor ⎛ ⎞ ...
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... AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A. Figure 6. Voltage Regulator Circuit CLOCK SIGNALS The ADSP-BF538/ADSP-BF538F processors can be clocked by an external crystal, a sine wave input buffered, shaped clock derived from an external clock oscillator external clock is used, it should be a TTL compatible signal and must not be halted, changed, or operated below the speci- fied frequency during normal operation ...
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... Table 9. Booting Modes BMODE1–0 Description 00 Execute from 16-bit external memory (bypass boot ROM) 01 Boot from 8-bit or 16-bit flash (ADSP-BF538 only) or Boot from on board flash (ADSP-BF538F only) 10 Boot from SPI serial master 11 Boot from SPI serial slave EEPROM /flash (8-,16-, or 24-bit address range, or Atmel ...
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... File (LDF), allowing the developer to move between the graphi- cal and textual environments. Analog Devices emulators use the IEEE 1149.1 JTAG Test Access Port of the ADSP-BF538/ADSP-BF538F processors to monitor and control the target board processor during emula- tion. The emulator provides full speed emulation, allowing Rev ...
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... All internal and I/O power supplies should be well bypassed with bypass capacitors placed as close to the ADSP- ® evaluation plat- BF538/ADSP-BF538F processors as possible. For further details on the on-chip voltage regulator and related board design guidelines, see the EE-228: Switching Regulator Design Considerations for ADSP-BF533 Blackfin Processors applications note on the Analog Devices web site log.com)— ...
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... ADSP-BF538/ADSP-BF538F PIN DESCRIPTIONS ADSP-BF538/ADSP-BF538F processor pin definitions are listed in Table 10. In order to maintain maximum functionality and reduce package size and pin count, some pins have dual, multi- Table 10. Pin Descriptions Pin Name I/O Memory Interface ADDR19–1 O DATA15–0 I/O ABE1–0/SDQM1–0 ...
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... GPIO SPI1 Master Out Slave In/GPIO SPI1 Master In Slave Out/GPIO SPI1 Clock/GPIO SPI1 Slave Select Input/GPIO SPI1 Slave Select Enable/GPIO SPI2 Master Out Slave In/GPIO SPI2 Master In Slave Out/GPIO Rev. PrD | Page May 2006 ADSP-BF538/ADSP-BF538F Driver Type ...
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... ADSP-BF538/ADSP-BF538F Table 10. Pin Descriptions (Continued) Pin Name I/O SCK2/PD7 I/O SPI2SS/PD8 I/O SPI2SEL/PD9 I/O RX1/PD10 I/O TX1/PD11 I/O RX2/PD12 I/O TX2/PD13 I/O Port E: SPORT2/SPORT3/GPIO RSCLK2/PE0 I/O RFS2/PE1 I/O DR2PRI /PE2 I/O DR2SEC/PE3 I/O TSCLK2/PE4 I/O TFS2/PE5 I/O DT2PRI/PE6 I/O DT2SEC/PE7 I/O RSCLK3/PE8 I/O RFS3/PE9 I/O DR3PRI/PE10 I/O DR3SEC/PE11 I/O TSCLK3/PE12 I/O TFS3/PE13 I/O DT3PRI/PE14 I/O DT3SEC/PE15 I/O Port F: Parallel Peripheral Interface Port/SPI0/Timers/GPIO SPI0SS/PF0 I/O SPI0SEL1/TMRCLK/PF1 I/O SPI0SEL2/PF2 ...
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... Non-maskable Interrupt (This pin should be pulled HIGH when not used.) Boot Mode Strap External FET Drive 0 External FET Drive 1 General-purpose regulator wakeup (This pin should be pulled HIGH when not used) I/O Power Supply Internal Power Supply Real Time Clock Power Supply Ground Rev. PrD | Page May 2006 ADSP-BF538/ADSP-BF538F Driver Type C C ...
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... ADSP-BF538/ADSP-BF538F SPECIFICATIONS Note that component specifications are subject to change without notice. OPERATING CONDITIONS 1 Parameter V Internal Supply Voltage DDINT V External Supply Voltage DDEXT V Real Time Clock Power Supply Voltage DDRTC 2 V High Level Input Voltage , @ High Level Input Voltage , @ V IHCLKIN ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-BF538/ADSP-BF538F processors feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... ADSP- BF538/ADSP-BF538F processor clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock, system clock and Voltage Controlled Oscillator Table 13. Core and System Clock Requirements—ADSP-BF538/ADSP-BF538F—500 MHz Parameter f Core Clock Frequency (V ...
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... ARDY DATA15–0 Figure 11. Asynchronous Memory Read Cycle Timing with Synchronous ARDY and Figure PROGRAMMED READ ACCESS 4 CYCLES BE, ADDRESS HARDY t SARDY Rev. PrD | Page May 2006 ADSP-BF538/ADSP-BF538F Min Max 2.1 0.8 TBD TBD 6.0 0.8 HOLD 1 CYCLE ACCESS EXTENDED 3 CYCLES HARDY ...
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... ADSP-BF538/ADSP-BF538F Table 17. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY Parameter Timing Requirements t DATA15–0 Setup Before CLKOUT SDAT t DATA15–0 Hold After CLKOUT HDAT t ARDY Negated Delay from AMSx Asserted DANR t ARDY Asserted Hold After ARE Negated HAA t Output Delay After CLKOUT ...
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... Figure 13. Asynchronous Memory Write Cycle Timing with Synchronous ARDY and Figure ACCESS PROGRAMMED WRITE HOLD EXTENDED ACCESS 2 CYCLES 1 CYCLE 1 CYCLE SARDY t t HARDY HARD Y Rev. PrD | Page May 2006 ADSP-BF538/ADSP-BF538F Min Max TBD TBD 6.0 1.0 6.0 0 DDAT Unit ...
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... ADSP-BF538/ADSP-BF538F Table 19. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY Parameter Timing Requirements t ARDY Negated Delay from AMSx Asserted DANR t ARDY Asserted Hold After ARE Negated HAA Switching Characteristics t DATA15–0 Disable After CLKOUT DDAT t DATA15–0 Enable After CLKOUT ENDAT ...
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... DATA(OUT) CMND ADDR (OUT SCLK t SSDAT t HSDAT t DCAD t ENSDAT t DCAD t HCAD NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE. Figure 15. SDRAM Interface Timing Rev. PrD | Page May 2006 ADSP-BF538/ADSP-BF538F Min Max 2.1 0.8 7.5 2.5 2.5 6.0 0.8 6.0 1.0 t SCLKH t SCLKL t D SDA T t HCAD Unit ns ...
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... ADSP-BF538/ADSP-BF538F External Port Bus Request and Grant Cycle Timing Table 21 and Table 22 on Page 31 and Figure 16 on Page 31 describe external port bus request and grant cycle operations for synchronous and for asynchronous BR. Table 21. External Port Bus Request and Grant Cycle Timing with Synchronous BR ...
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... CLKOUT High to BGH Deasserted Hold Time EBH CLKOUT BR AMSx ADDR19-1 ABE1-0 AWE ARE BG BGH Figure 17. External Port Bus Request and Grant Cycle Timing with Asynchronous BR t WBR Rev. PrD | Page May 2006 ADSP-BF538/ADSP-BF538F Min Max SCLK 4.5 4.5 3.6 3.6 3.6 3 DBG t EBG ...
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... ADSP-BF538/ADSP-BF538F Parallel Peripheral Interface Timing Table 23 and Figure 18, Figure 19, Figure describe Parallel Peripheral Interface operations. Table 23. Parallel Peripheral Interface Timing Parameter Timing Requirements t PPI_CLK Width PCLKW 1 t PPI_CLK Period PCLK t External Frame Sync Setup Before PPI_CLK SFSPE t External Frame Sync Hold After PPI_CLK ...
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... DATA0 SAMPLED t HFSPE t SFSPE t HDRPE Figure 19. PPI GP Rx Mode with External Frame Sync Timing FRAME DATA0 IS SYNC IS DRIVEN SAMPLED OUT t HFSPE t SFSPE t HDTPE DATA0 t DDTPE Figure 20. PPI GP Tx Mode with External Frame Sync Timing Rev. PrD | Page May 2006 ADSP-BF538/ADSP-BF538F ...
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... ADSP-BF538/ADSP-BF538F FRAME SYNC IS REFERENCED TO THIS CLOCK EDGE PPI_CLK POLC = 0 PPI_CLK POLC = 1 t DFSPE t HOFSPE POLS = 1 PPI_FS1 POLS = 0 POLS = 1 PPI_FS2 POLS = 0 PPI_DATA DATA0 IS DRIVEN OUT t DDTPE t HDTPE DATA0 Figure 21. PPI GP Tx Mode with Internal Frame Sync Timing Rev. PrD | Page May 2006 ...
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... Data Enable Delay from Internal TSCLK DTENI t Data Disable Delay from Internal TSCLK DDTTI 1 Referenced to drive edge. Figure 22 on Page Rev. PrD | Page May 2006 ADSP-BF538/ADSP-BF538F Min Max 1 3.0 1 3.0 3.0 3.0 4.5 15.0 2 10.0 2 0.0 10.0 0.0 Min Max 1 8.0 1 –2.0 6 ...
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... ADSP-BF538/ADSP-BF538F Table 27. External Late Frame Sync Parameter Switching Characteristics t Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 0 DDTLFSE t Data Enable from late FS or MCE = 1, MFD = 0 DTENLFS 1 MCE = 1, TFS enable and TFS valid follow t DTENLFS 2 If external RFS/TFS setup to RSCLK/TSCLK > t ...
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... SFSE/I t DDTE DTENLFSE HDTE/I 1ST BIT t DDTLFSE DRIVE SAMPLE DRIVE t SFSE/I t DDTE DTENLFSE HDTE/I 1ST BIT t DDTLFSE Figure 23. External Late Frame Sync (Frame Sync Setup < t Rev. PrD | Page May 2006 ADSP-BF538/ADSP-BF538F 2ND BIT t HOFSE/I 2ND BIT /2) SCLKE ...
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... ADSP-BF538/ADSP-BF538F EXTERNAL RFS WITH MCE = 1, MFD = 0 RSCLK RFS DT LATE EXTERNAL TFS TSCLK TFS DT DRIVE SAMPLE DRIVE t t SFSE/I HOFSE/I t DDTE HDTE/I DTENLSCK 1ST BIT t DDTLSCK DRIVE SAMPLE DRIVE t t SFSE/I HOFSE/I t DDTE DTENLSCK HDTE/I 1ST BIT t DDTLSCK Figure 24. External Late Frame Sync (Frame Sync Setup > t Rev ...
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... SPICLM SPICHM t t DDSPIDM HDSPIDM MSB t HSPIDM MSB VALID t DDSPIDM MSB t HSPIDM LSB VALID Figure 25. Serial Peripheral Interface (SPI) Port—Master Timing Rev. PrD | Page May 2006 ADSP-BF538/ADSP-BF538F Min Max 7.5 –1.5 2t –1.5 SCLK 2t –1.5 SCLK 2t –1.5 SCLK 4t –1.5 SCLK 2t –1.5 ...
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... ADSP-BF538/ADSP-BF538F Serial Peripheral Interface Port—Slave Timing Table 29 and Figure 26 describe SPI port slave operations. Table 29. Serial Peripheral Interface (SPI) Port—Slave Timing Parameter Timing Requirements t Serial Clock High Period SPICHS t Serial Clock low Period SPICLS t Serial Clock Period SPICLK t Last SCK Edge to SPI0SS Not Asserted ...
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... GP Port Pin Input Pulse Width WFI Switching Characteristic t GP Port Pin Output Delay From CLKOUT Low GPOD CLKOUT GPP OUTPUT GPP INPUT t GPOD t WFI Figure 27. Programmable Flags Cycle Timing Rev. PrD | Page May 2006 ADSP-BF538/ADSP-BF538F Min Max SCLK 0 6 Unit ns ns ...
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... ADSP-BF538/ADSP-BF538F Timer Cycle Timing Table 31 and Figure 28 describe timer expired operations. The input signal is asynchronous in “width capture mode” and “external clock mode” and has an absolute maximum input fre- quency MHz. SCLK Table 31. Timer Cycle Timing Parameter Timing Characteristics ...
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... TCK TMS TDI TDO SYSTEM INPUTS t SYSTEM OUTPUTS TCK t t STAP HTAP t DTDO t t SSYS HSYS DSYS Figure 29. JTAG Port Timing Rev. PrD | Page May 2006 ADSP-BF538/ADSP-BF538F Min Max Unit TCK ns ns ...
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... ADSP-BF538/ADSP-BF538F OUTPUT DRIVE CURRENTS Figure 30 through Figure 37 on Page 45 voltage characteristics for the output drivers of the ADSP- BF538/ADSP-BF538F processors. The curves represent the cur- rent drive capability of the output drivers as a function of output voltage. 120 100 ...
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... 2.75V @ - 40° -20 - -40 -50 - -70 -80 2 3.0 ) DDEXT Rev. PrD | Page May 2006 ADSP-BF538/ADSP-BF538F 0.5 1.0 1.5 2.0 2.5 SOURCE VOLTAGE (V) Figure 37. Drive Current D (High V DDEXT 0.5 1.0 1 ...
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... Many operating conditions can affect power dissipation. System designers should refer to EE-TBD: Estimating Power for ADSP-BF538/ADSP-BF538F Blackfin Processors.” This docu- ment will provide detailed information for optimizing your design for lowest power. Table 33. Internal Power Dissipation (Hibernate mode) ...
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... To determine the data output hold time in a particular system, using the equation given above. Choose ΔV first calculate t DECAY to be the difference between the ADSP-BF538/ADSP-BF538F processor’s output voltage and the input threshold for the device requiring the hold time the total bus capacitance ...
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... ADSP-BF538/ADSP-BF538F CLKOUT (CLKOUT DRIVER), V (MIN) = 2.25V, TEMPERATURE = 85 ° C DDEXT 12 10 RISE TIME 100 LOAD CAPACITANCE (pF) Figure 45. Typical Output Delay or Hold for Driver CLKOUT (CLKOUT DRIVER), V (MAX) = 3.65V, TEMPERATURE = 85°C DDEXT RISE TIME ...
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... FALL TIME 150 200 250 MAX DDEXT Figure 52. Typical Output Delay or Hold for Driver Rev. PrD | Page May 2006 ADSP-BF538/ADSP-BF538F PH0 V (MAX) = 3.65V, TEMPERATURE = 85°C DDEXT RISE TIME FALL TIME 100 150 LOAD CAPACITANCE (pF) PH0 V (MAX) = 3.65V, TEMPERATURE = 85° ...
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... ADSP-BF538/ADSP-BF538F THERMAL CHARACTERISTICS To determine the junction temperature on the application printed circuit board use: ( Ψ CASE JT where Junction temperature ( Case temperature ( C) measured by customer at top CASE center of package. Ψ = From Table Power dissipation (see Power Dissipation on Page 46 D the method to calculate P ...
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... FLASH CONTROL Figure 54. 316-Ball Mini-BGA Pin Configuration (Bottom View) Rev. PrD | Page May 2006 ADSP-BF538/ADSP-BF538F GND VDDINT VDDRTC NC FLASH CONTROL VDDEXT VROUTx I/O A1 BALL ...
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... ADSP-BF538/ADSP-BF538F Table 37. 316-Ball Mini-BGA Pin Assignment (Numerically by Pin Number) Ball No. Signal Ball No. Signal A1 GND C7 SPI2SEL F8 A2 PF10 C8 SPI2SS A3 PF11 C9 MOSI2 A4 PPI_CLK C10 MISO2 A5 PPI0 C11 SCK2 A6 PPI2 C12 VDDINT F13 A7 PF15 C13 SPI1SEL F14 A8 PF13 C14 MISO1 A9 VDDRTC C15 SPI1SS A10 ...
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... PPI0 GND K7 GND U3 PPI1 GND K8 GND V2 PPI2 GND K9 GND V3 PPI3 GND K10 GND V6 RESET Rev. PrD | Page May 2006 ADSP-BF538/ADSP-BF538F Ball No. Signal Ball No. Signal V17 RFS0 P2 TX0 V18 RFS1 K1 TX1 C6 W2 RFS2 Y11 TX2 W19 RFS3 T18 VDDEXT K3 Y1 RSCK0 ...
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... ADSP-BF538/ADSP-BF538F OUTLINE DIMENSIONS Dimensions in Figure 55—316-Ball Mini Ball Grid Array (BC-316) are shown in millimeters. 17.00 BSC SQ A1 BALL INDICATOR TOP VIEW 1.70 SIDE VIEW 1.61 1.46 DETAIL A NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. COMPLIANT TO JEDEC REGISTERED OUTLINE MO-205, VARIATION AM, WITH THE EXCEPTION OF BALL DIAMETER. 3. CENTER DIMENSIONS ARE NOMINAL. ...
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... MHz ADSP-BF538BBCZ-4F8 –40ºC to +85ºC 400 MHz ADSP-BF538BBCZ-5A –40ºC to +85ºC 500 MHz ADSP-BF538BBCZ-5F4 –40ºC to +85ºC 500 MHz ADSP-BF538BBCZ-5F8 –40ºC to +85ºC 500 MHz Pb-free part. 2 Referenced temperature is ambient temperature. Solder Mask ...
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... ADSP-BF538/ADSP-BF538F ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06172-0-5/06(PrD) Rev. PrD | Page May 2006 Preliminary Technical Data ...