ADSP21020 AD [Analog Devices], ADSP21020 Datasheet
ADSP21020
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ADSP21020 Summary of contents
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FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 30 ns, 33.3 MIPS Instruction Rate, Single-Cycle Execution 100 MFLOPS Peak, 66 MFLOPS Sustained Performance 1024-Point Complex FFT Benchmark: 0.58 ms Divide (y/x): 180 ns Inverse Square ...
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ADSP-21020 • Instruction Cache The ADSP-21020 includes a high performance instruction cache that enables three-bus operation for fetching an instruction and two data values. The cache is selective—only the instructions whose fetches conflict with program memory data accesses are cached. ...
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DAG PMD BUS BUS CONNECT DMD BUS FLOATING & FIXED-POINT MULTIPLIER, FIXED-POINT ACCUMULATOR the standard IEEE format, whereas the 40-bit IEEE extended- precision format has eight additional LSBs of mantissa for greater accuracy. The ...
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ADSP-21020 in a specified register, either before (premodify) or after (postmodify) the access. To implement automatic modulo addressing for circular buffers, the ADSP-21020 provides buffer length registers that can be associated with each pointer. Base values for pointers allow circular ...
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SELECTS PROGRAM MEMORY The ADSP-21020 also implements on-chip emulation through the JTAG test access port. The processor’s eight sets of break- point range registers enable program execution at full speed until reaching a desired break-point address range. The processor can ...
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ADSP-21020 Pin Name Type Function DMPAGE O Data Memory Page Boundary. The ADSP- 21020 asserts this pin to signal that a data memory page boundary has been crossed. Memory pages must be defined in the memory control registers. DMTS I/S ...
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COMPUTE AND MOVE OR MODIFY INSTRUCTIONS 1. compute condition compute; 3a. IF condition compute, 3b. IF condition compute, 3c. IF condition compute, 3d. IF condition compute, 4a. IF condition compute, 4b. IF condition compute, 4c. IF condition compute, ...
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ADSP-21020 IMMEDIATE MOVE INSTRUCTIONS 14a. DM(<addr32>) = ureg ; PM(<addr24>) 14b. ureg = DM(<addr32>) ; PM(<addr24>) 15a. DM(<data32>, Ia) = ureg; PM(< data24>, Ic) 15b. ureg = DM(<data32>, Ia) ; PM(<data24>, Ic) 16. DM(Ia, Mb) = <data32>; PM(Ic, Md) 17. ...
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Table III. Universal Registers Name Function Register File R15–R0 Register file locations Program Sequencer PC* Program counter; address of instruction cur- rently executing PCSTK Top of PC stack PCSTKP PC stack pointer FADDR* Fetch address DADDR* Decode address LADDR Loop ...
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ADSP-21020 Table V. Multiplier Compute Operations MRF = MRB = MRF + Rx * ...
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Table Vll. Multifunction Compute Operations Fixed-Point Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12 Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 – R15-12 Rm=R3-0 * R7-4 (SSFR), Ra=(R11-8 + R15-12)/2 MRF=MRF + R3-0 * R7-4 (SSF), Ra=R11-8 + R15-12 MRF=MRF + R3-0 * ...
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ADSP-21020–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter V Supply Voltage DD T Ambient Operating Temperature AMB Refer to Environmental Conditions for information on thermal specifications. ELECTRICAL CHARACTERISTICS Parameter 1 V Hi-Level Input Voltage Hi-Level Input Voltage IHCR 1, ...
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TIMING PARAMETERS General Notes See Figure 15 on page 24 for voltage reference levels. Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful ...
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ADSP-21020 Interrupts Parameter Timing Requirement: t IRQ3-0 Setup before CLKIN High 38 SIR t IRQ3-0 Hold after CLKIN High HIR t IRQ3-0 Pulse Width IPW NOTE * – Meeting setup and hold guarantees interrupts will ...
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Flags Parameter 1 Timing Requirement: t FLAG3-0 Setup before CLKIN High SFI IN t FLAG3-0 Hold after CLKIN High HFI IN t FLAG3-0 Delay from xRD, xWR Low DWRFI IN t FLAG3-0 Hold after xRD, xWR HFIWR IN Deasserted Switching ...
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ADSP-21020 Bus Request/Bus Grant Parameter Timing Requirement Hold after CLKIN High HBR t BR Setup before CLKIN High SBR Switching Characteristic: t Memory Interface Disable to BG Low –2 DMDBGL t CLKIN High to Memory Interface DME Enable ...
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External Memory Three-State Control Parameter Timing Requirement: t xTS, Setup before CLKIN High STS t xTS Delay after Address, Select DADTS t xTS Delay after XRD, XWR Low DSTS Switching Characteristic: t Memory Interface Disable before DTSD CLKIN High t ...
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ADSP-21020 Memory Read Parameter Timing Requirement: t Address, Select to Data Valid DAD t xRD Low to Data Valid DRLD t Data Hold from Address, Select HDA t Data Hold from xRD High HDRH t xACK Delay from Address DAAK ...
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CLKIN ADDRESS, SELECT t DAP DMPAGE, PMPAGE t DCKRL DMRD, PMRD DATA DMACK, PMACK DMWR, PMWR REV DARL RW t DRLD t DAD t DRAK t t SAK DAAK Figure 10. Memory Read –19– ADSP-21020 t HDA ...
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ADSP-21020 Memory Write Parameter Timing Requirement: t xACK Delay from Address, Select DAAK t xACK Delay from xWR Low DWAK t xACK Setup before CLKIN High SAK t xACK Hold after CLKIN High HAK Switching Characteristic: t Address, Select to ...
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CLKIN ADDRESS, SELECT DMPAGE, PMPAGE DMWR, PMWR t DCKWL DATA DMACK, PMACK DMRD, PMRD REV DAP t DAWH t t DAWL WW t WDE t DWAK t t DAAK SAK Figure 11. Memory Write –21– ADSP-21020 t DWHA ...
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ADSP-21020 IEEE 1149.1 Test Access Port Parameter Timing Requirement: t TCK Period TCK t TDI, TMS Setup before TCK High STAP t TDI, TMS Hold after TCK High HTAP t System Inputs Setup before TCK High 7 SSYS t System ...
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TCK t STAP TMS,TDI TDO t SSYS SYSTEM INPUTS SYSTEM OUTPUTS REV TCK t HTAP t DTDO t HSYS t DSYS Figure 12. IEEE 1149.1 Test Access Port –23– ADSP-21020 ...
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ADSP-21020 TEST CONDITIONS Output Disable Time Output pins are considered to be disabled when they stop driving, go into a high-impedance state, and start to decay from their output high or low voltage. The time for the voltage on the ...
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Capacitive Loading Output delays are based on standard capacitive loads: 100 pF on address, select, page and strobe pins, and all others (see Figure 14). For different loads, these timing parameters should be derated. See the Hardware ...
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ADSP-21020 ENVIRONMENTAL CONDITIONS The ADSP-21020 is available in a Ceramic Pin Grid Array (CPGA). The package uses a cavity-down configuration which gives it favorable thermal characteristics. The top surface of the package contains a raised copper slug from which much ...
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All GND pins should have a low impedance path to ground. A ground plane is required in ADSP-21020 systems to reduce this impedance, minimizing noise. The EVDD and IVDD pins should be bypassed to the ground plane using approximately 14 ...
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ADSP-21020 PMA17 PMA20 TMS EGND U TCK T EGND PMA19 PMA23 PMS1 TRST S PMA11 PMA14 PMA18 PMA22 PMPAGE R EGND PMA10 PMA15 PMA16 PMA21 P PMA8 PMA9 PMA13 PMA12 N EVDD PMA5 PMA6 PMA7 ...
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U PMD31 PMD35 PMD39 PMD40 EGND PMD27 PMD30 PMD32 PMD37 PMD21 PMD26 PMD28 PMD34 PMD36 R EGND PMD23 PMD25 PMD29 PMD33 P PMD18 PMD19 PMD22 PMD24 N EVDD PMD16 PMD17 PMD20 M ...
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ADSP-21020 PGA PIN LOCATION NAME G16 DMA0 G17 DMA1 F18 DMA2 F17 DMA3 F16 DMA4 F15 DMA5 E18 DMA6 E17 DMA7 E16 DMA8 D18 DMA9 E15 DMA10 D17 DMA11 D16 DMA12 C18 DMA13 C17 DMA14 D15 DMA15 B18 DMA16 B17 ...
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SYMBOL NOTE When socketing the CPGA package, use of a low insertion force socket is recommended. REV. C OUTLINE DIMENSIONS Dimensions shown ...
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ADSP-21020 Ambient Temperature Part Number* Range ADSP-21020KG- +70 C ADSP-21020KG-100 +70 C ADSP-21020KG-133 +70 C ADSP-21020BG-80 – +85 C ADSP-21020BG-100 – +85 C ADSP-21020BG-120 – ...