SAA7124WP PHILIPS [NXP Semiconductors], SAA7124WP Datasheet - Page 15

• Manufacturer Part Number: SAA7124WP
• Description: Digital Video Encoder ECO-DENC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
If there are missing pulses at RCV1 and/or RCV2, the time
base of ECO-DENC runs free, thus an arbitrary number of
synchronization slopes may miss, but no additional pulses
(with the incorrect phase) must occur.
If the vertical and horizontal phase is derived from RCV1,
RCV2 can be used for horizontal or composite blanking
input or output.
Alternatively, the device can be triggered by auxiliary
codes in a “CCIR 656” data stream at the MP port.
In the master mode, the time base of the circuit
continuously runs free. On the RCV1 port, the IC can
output:
On the RCV2 port, the IC can provide a horizontal pulse
with programmable start and stop phase; this pulse can be
inhibited in the vertical blanking period to build up, for
example, a composite blanking signal.
The polarity of both RCV1 and RCV2 is selectable by
software control.
Field length is in accordance with to 50 Hz or 60 Hz
standards, including non-interlaced options; start and end
of its active part can be programmed. The active part of a
field always starts at the beginning of a line, If the standard
blanking option SBLBN is not set.
Table 2 8-bit multiplexed format (similar to “CCIR 656” )
1996 Nov 07
Sample
Luminance pixel number
Colour pixel number
A Vertical Sync signal (VS) with 3 or 2.5 lines duration,
or;
An ODD/EVEN signal which is LOW in odd fields, or;
A field sequence signal (FSEQ) which is HIGH in the first
of 4, 8 fields respectively.
Digital Video Encoder (ECO-DENC)
TIME
Cb
0
0
0
Y
1
0
0
15
Cr
2
I
The I
supporting 7-bit slave addresses and 400 kbits/s
guaranteed transfer rate. It uses 8-bit subaddressing with
an auto-increment function. All registers are write only,
except one readable status byte.
Two I
Input levels and formats
ECO-DENC expects digital Y, Cb, Cr data with levels
(digital codes) in accordance with “CCIR 601” .
For C and CVBS outputs, deviating amplitudes of the
colour difference signals can be compensated by
independent gain control setting, while gain for luminance
is set to predefined values, distinguishable for 7.5 IRE
set-up or without set-up.
For RGB (or Y, Cb and Cr) outputs fixed amplification in
accordance with “CCIR 601” is provided.
Reference levels are measured with a colour bar,
100% white, 100% amplitude and 100% saturation.
T
R = Y + 1.3707
G = Y
B = Y + 1.7324
Representation of R, G and B at the output is 9 bits at
27 MHz.
0
2
RANSFORMATION
C-bus interface
88H: LOW at pin SA
8CH: HIGH at pin SA.
1
2
2
C-bus interface is a standard slave transceiver,
C-bus slave addresses are selected:
0.3365
Y
2
1
BITS
(Cb
(Cr
(Cb
Cb
4
2
128)
128).
128)
SAA7124; SAA7125
2
Y
5
0.6982
2
Preliminary specification
2
Cr
(Cr
6
2
128)
3
Y
7
3