SAA7183AWP PHILIPS [NXP Semiconductors], SAA7183AWP Datasheet - Page 6

• Manufacturer Part Number: SAA7183AWP
• Description: Digital Video Encoder EURO-DENC2
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
PINNING
1996 Oct 02
RESET
n.c.
V
SA
V
OVL2
OVL1
OVL0
KEY
DP0
DP1
DP2
DP3
V
V
DP4
DP5
DP6
DP7
TTXRQ
TTX
V
n.c.
V
MP7
MP6
MP5
MP4
V
V
MP3
MP2
MP1
MP0
RCV1
RCV2
SYMBOL
SSD1
DDD1
DDD2
SSD2
DDD3
SSD3
DDD4
SSD4
Digital Video Encoder (EURO-DENC2)
PLCC84
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
11
1
2
3
4
5
6
7
8
9
PIN
QFP80
73
75
13
77
78
79
80
14
10
12
28
20
15
16
17
18
19
29
21
22
23
24
25
26
11
6
1
2
3
4
5
7
8
9
Reset input, active LOW. After reset is applied, all digital I/Os are in input mode.
The I
not connected
digital ground 1
The I
HIGH = 8CH.
digital supply voltage 1 (3.3 V)
3-bit overlay data input. This is the index for the internal look-up table.
Key input for OVL. When HIGH it selects OVL input.
Lower 4 bits of the data port. Input for multiplexed Cb, Cr data if 16 line input mode
is used.
digital supply voltage 2 (5 V)
digital ground 2
Upper 4 bits of the data port. Input for multiplexed Cb, Cr data if 16 line input mode
is used.
Teletext request output, indicating when bit stream is valid.
Teletext bit stream input.
digital supply voltage 3 (3.3 V)
not connected
digital ground 1
Upper 4 bits of MPEG port. It is an input for “ CCIR 656 ” style multiplexed Cb, Y, Cr
data, or for Y data only, if 16 line input mode is used.
digital supply voltage 4 (5 V)
digital ground 4
Lower 4 bits of MPEG port. It is an input for “ CCIR 656 ” style multiplexed Cb, Y, Cr
data, or for Y data only, if 16 line input mode is used.
Raster Control 1 for video port. This pin receives/provides a VS/FS/FSEQ signal.
Raster Control 2 for video port. This pin provides an HS pulse of programmable
length or receives an HS pulse.
2
2
C-bus receiver waits for the START condition.
C-bus slave address select input pin. LOW: slave address = 88H,
6
DESCRIPTION
SAA7182A; SAA7183A
Preliminary specification