ADMCF326 AD [Analog Devices], ADMCF326 Datasheet
ADMCF326
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ADMCF326 Summary of contents
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... PROGRAM DATA RAM MEMORY 512 24 512 16 PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY DATA POR TIMER 28-Lead Flash Memory DSP Motor Controller ADMCF326 PWMTRIP 16-BIT 6 VREF THREE- ANALOG 2.5V PHASE INPUTS PWM SERIAL PORT 2 8-BIT WATCH- 9-BIT AUX ...
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... ADMCF326–SPECIFICATIONS ANALOG-TO-DIGITAL CONVERTER Parameter Signal Input 1 Resolution 2 Linearity Error 2 Zero Offset Channel-to-Channel Comparator Match Comparator Delay 2 ADC High Level Input Current 2 ADC Low Level Input Current NOTES 1 Resolution varies with PWM switching frequency (double update mode) 78.1 kHz = 8 bits, 4.9 kHz = 12 bits. ...
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... Read Operating Temperature Specifications subject to change without notice. Min Typ Max Unit 2.40 2.50 2.60 V 2.45 2.50 2. ppm/°C Min Typ Max Unit 3.2 3.7 4.2 V 100 mV 1 3.2 ms Min Typ Max Unit 10,000 Cycles 15 Years –40 +85 C ADMCF326 Conditions/Comments T = 25°C to 85°C SOIC A Conditions/Comments Conditions/Comments Cycle = Erase/Program/Verify ...
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... ADMCF326 TIMING PARAMETERS Parameter Clock Signals Signal t is defined as 0 The ADMCF326 uses an input clock with a CK CKIN frequency equal to half the instruction rate MHz input clock (which is equivalent to 100 ns) yields processor cycle (equivalent to 20 MHz). When t values are within the range of 0.5 t ...
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... FRAME MODE) RFS (MULTICHANNEL MODE, FRAME DELAY 0 [MFD = 0]) OUT SCS SCH SCDV t t SCDH SCDE t TDE t TDV t RDV ADMCF326 Min Max 100 0. SCK t SCP t SCP t SCDD Unit ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADMCF326 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... MIPS, fixed-point DSP core with a complete set of motor control and system peripherals that permits fast, efficient devel- opment of motor controllers. The DSP core of the ADMCF326 is the ADSP-2171, which is completely code-compatible with the ADSP-21xx DSP family and combines three computational units, data address generators and a program sequencer ...
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... Operation from external program memory is described in detail in the ADSP- 2100 Family User’s Manual, Third Edition. The ADMCF326 writes data from its 16-bit registers to the 24-bit program memory using the PX register to provide the lower eight bits. When it reads data (not instructions) from 24-bit program memory to a 16-bit data register, the lower eight bits are placed in the PX register ...
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... PWMTRIP). All motor control interrupts are multiplexed into the DSP core through the peripheral IRQ2 interrupt. The interrupts are internally prioritized and individually maskable. A detailed description of the entire interrupt system of the ADMCF326 is presented later, following a more detailed description of each peripheral block. ...
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... CLKIN ADMCF326 RESET Clock Signals The ADMCF326 can be clocked either by a crystal or a TTL- compatible clock signal. For normal operation, the CLKIN input cannot be halted, changed during operation, or operated below the specified minimum frequency external clock is used, it should be a TTL-compatible signal running at half the instruction rate ...
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... The configuration of both the SYSCNTL and MEMWAIT reg- isters of the ADMCF326 are shown at the end of the data sheet. THREE-PHASE PWM CONTROLLER Overview The PWM generator block of the ADMCF326 is a flexible, ...
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... ADMCF326 A functional block diagram of the PWM controller is shown in Figure 6. The generation of the six output PWM signals on pins controlled by four important blocks: • The three-phase PWM timing unit, which is the core of the PWM controller, generates three pairs of complemented and dead-time-adjusted center-based PWM signals. ...
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... The dead time can be programmed to zero by writing 0 to the PWMDT register. PWM Operating Mode: MODECTRL and SYSSTAT Registers The PWM controller of the ADMCF326 can operate in two dis- tinct modes: single update mode and double update mode. The operating mode of the PWM controller is determined by the state of Bit 6 of the MODECTRL register ...
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... ADMCF326 over half the PWM period. The switching signals produced by the three-phase timing unit are also adjusted to incorporate the programmed dead time value in the PWMDT register. The PWM is center-based. This means that in single update mode the resulting output waveforms are symmetrical and centered in the PWMSYNC period. Figure 7 presents a typical PWM tim- ing diagram illustrating the PWM-related registers’ ...
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... Therefore, by programming identical duty cycles for two PWM channels (for example, let PWMCHA = PWMCHB) and setting Bit 7 of the PWMSEG register to crossover the BH/BL pair of PWM signals possible to turn ON the high-side switch of Phase A and the low-side switch of Phase B at the ADMCF326 ...
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... PWM Shutdown In the event of external fault conditions essential that the PWM system be instantaneously shut down. Two methods of sensing a fault condition are provided by the ADMCF326. For the first method, a low level on the PWMTRIP pin initiates an instantaneous, asynchronous (independent of DSP clock) shutdown of the PWM controller. This places all six PWM ...
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... The parameters of the PWM block are tabu- lated in Table V. ADC OVERVIEW The ADC of the ADMCF326 is based upon the single slope conversion technique. This approach offers an inherently monotonic conversion process and to within the noise and stability of its components, and there will be no missing codes. ...
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... Programmable Current Source The ADMCF326 has an internal current source that is used to charge an external capacitor, generating the voltage ramp used for conversion. The magnitude of the output of the current source circuit is subject to manufacturing variations and can vary from one device to the next. Therefore, the ADMCF326 ...
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... PWM output signals can be used as simple single-bit digital-to- analog converters. The auxiliary PWM system of the ADMCF326 can operate in two different modes: independent mode or offset mode. The operating mode of the auxiliary PWM system is controlled by Bit 8 of the MODECTRL register ...
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... DSP core and motor control peripheral reset is performed. In addition, Bit 1 of the SYSSTAT register is set so that after a watchdog reset, the ADMCF326 can determine that the reset was due to the timeout of the watchdog timer and not an external reset. Following a watchdog reset, Bit 1 of the SYSSTAT register may be cleared by writing zero to the WDTIMER register ...
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... IRQ2 interrupt enable bit (Bit 9) of the IMASK register must be set. The configuration of the IMASK register of the ADMCF326 is shown at the end of the data sheet. Interrupt Configuration The IFC and ICNTL registers of the DSP core control and config- ure the interrupt controller of the DSP core ...
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... IFC and ICNTL registers is shown at the end of the data sheet. Interrupt Operation Following a reset, the ROM code on the ADMCF326 must copy a default interrupt vector table into program memory RAM from address 0x0000 to 0x002F. Since each interrupt source has a dedicated four-word space in this vector table possible to code short interrupt service routines (ISR) in place ...
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... Reserved [ PIO0 to PIO7 Mode Select Reserved [ PWMSYNC Pulsewidth [0] PWM S/W Trip Bit Reserved [2. . .0] ICONST_TRIM Reserved [15. . .0] Flash Memory Control Register [11. . .0] Flash Memory Address Register [13. . .0] Flash Memory Data Register High [15. . .0] Flash Memory Data Register Low Reserved ADMCF326 ...
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... ADMCF326 Address Name 0x3FFF SYSCNTL 0x3FFE MEMWAIT 0x3FFD TPERIOD 0x3FFC TCOUNT 0x3FFB TSCALE 0x3FFA . . . F3 0x3FF2 SPORT1_CTRL_REG 0x3FF1 SPORT1_SCLKDIV 0x3FF0 SPORT1_RFSDIV 0x3FEF SPORT1_AUTOBUF_CTRL Table XI. DSP Core Registers Bits [ [ [ [ [ [ [ [ Function System Control Register Memory Wait State Control Register ...
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... FLASH MEMORY DATA REGISTER HIGH (FMDRH DATA 23–8 MOST SIGNIFICANT BIT IS ON THE LEFT. FOR EXAMPLE, DATA23 IS BIT 15 OF FMDRH. ADMCF326 0x2080 ...
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... ADMCF326 CHANNEL CROSSOVER CROSSOVER B CHANNEL CROSSOVER 1 = CROSSOVER C CHANNEL CROSSOVER Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written as shown ...
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... PWMCHA (R/ PWMCHB (R/ PWMCHC (R/ ADMCF326 (0x200A) PWMPD PWMPD = T SECONDS MIN f CLKOUT (0x200B GDCLK GATE DRIVE CHOPPING FREQUENCY f CLKOUT f = CHOP 4 (GDCLK + ...
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... ADMCF326 Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written as shown ...
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... PIO0 – PIO7 PIOFLAG1 ( PIO8 ADMCF326 (0x2006 INTERRUPT DISABLE 1 = INTERRUPT ENABLE (0x2046 INTERRUPT DISABLE 1 = INTERRUPT ENABLE (0x2007 INTERRUPT 1 = INTERRUPT FLAGGED ...
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... ADMCF326 Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written as shown. ...
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... ICONST_TRIM (R/ ICONST MIN = BITS 0 – 2 CLEARED. ICONST MAX = BITS 0 – 2 SET. ADMCF326 (0x2000 (0x2001 (0x2002 (0x2003 ...
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... ADMCF326 OFFSET MODE AUXILIARY 1 = INDEPENDENT MODE PWM SELECT ADC 0 = CLKIN RATE COUNTER 1 = CLKOUT RATE SELECT 1ST HALF OF PWM CYCLE 1 = 2ND HALF OF PWM CYCLE Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written as shown ...
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... IMASK (R/ ADMCF326 0 = LEVEL 1 = EDGE DSP REGISTER INTERRUPT CLEAR TIMER SPORT1 RECEIVE OR IRQ0 SPORT1 TRANSMIT OR IRQ1 SOFTWARE 0 SOFTWARE 1 IRQ2 DSP REGISTER TIMER SPORT1 RECEIVE ...
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... ADMCF326 0 = DISABLED SPORT1 ENABLE 1 = ENABLED Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written as shown. SYSCNTL (R/ ...
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... OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Wide-Body SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70 PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0500 0.0192 (0.49) 0.0118 (0.30) SEATING 0.0125 (0.32) (1.27) 0.0138 (0.35) 0.0040 (0.10) PLANE BSC 0.0091 (0.23) ADMCF326 0.0291 (0.74 0.0098 (0.25) 0.0500 (1.27 0.0157 (0.40) ...
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