PALCE22V10 LATTICE [Lattice Semiconductor], PALCE22V10 Datasheet

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PALCE22V10

Manufacturer Part Number
PALCE22V10
Description
24-Pin EE CMOS (Zero Power) Versatile PAL Device
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet

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DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The PALCE22V10 provides user-programmable logic for replacing conventional SSI/MSI gates and
flip-flops at a reduced chip count.
The PALCE22V10Z is an advanced PAL
erasable CMOS technology. It provides user-programmable logic for replacing conventional zero-
power CMOS SSI/MSI gates and flip-flops at a reduced chip count.
The PALCE22V10Z provides zero standby power and high speed. At 30 µA maximum standby
current, the PALCE22V10Z allows battery-powered operation for an extended period.
The PAL device implements the familiar Boolean logic transfer function, the sum of products. The
PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed
to create custom product terms, while the OR array sums selected terms at the outputs.
The product terms are connected to the fixed OR array with a varied distribution from 8 to16 across
the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each
macrocell can be programmed as registered or combinatorial, and active-high or active low. The
output configuration is determined by two bits controlling two multiplexers in each macrocell.
Publication# 16564
Amendment/0
As fast as 5-ns propagation delay and 142.8 MHz f
Low-power EE CMOS
10 macrocells programmable as registered or combinatorial, and active high or active low to
match application needs
Varied product term distribution allows up to 16 product terms per output for complex
functions
Peripheral Component Interconnect (PCI) compliant (-5/-7/-10)
Global asynchronous reset and synchronous preset for initialization
Power-up reset for initialization and register preload for testability
Extensive third-party software and programmer support
24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC
5-ns and 7.5-ns versions utilize split leadframes for improved performance
Rev: E
Issue Date: November 1998
PALCE22V10 and PALCE22V10Z
Families
24-Pin EE CMOS (Zero Power) Versatile PAL Device
PALCE22V10
PALCE22V10Z
®
device built with zero-power, high-speed, electrically-
COM'L: H-5/7/10/15/25,Q-10/15/25 IND: H-10/15/20/25
COM'L: -25
MAX
(external)
IND: -15/25

Related parts for PALCE22V10

PALCE22V10 Summary of contents

Page 1

... CMOS technology. It provides user-programmable logic for replacing conventional zero- power CMOS SSI/MSI gates and flip-flops at a reduced chip count. The PALCE22V10Z provides zero standby power and high speed µA maximum standby current, the PALCE22V10Z allows battery-powered operation for an extended period. ...

Page 2

... Product terms with all connections opened assume the logical HIGH state; product terms connected to both true and complement of any single input assume the logical LOW state. The PALCE22V10 has 12 inputs and 10 I/O macrocells. The macrocell (Figure 1) allows one of four potential output configurations registered output or combinatorial I/O, active high or active low (see Figure 1). The confi ...

Page 3

... Variable Input/Output Pin Ratio The PALCE22V10 has twelve dedicated input lines, and each macrocell output can be an I/O pin. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Unused input pins should be tied CLK Registered Output Configuration Each macrocell of the PALCE22V10 includes a D-type fl ...

Page 4

... Preset/Reset For initialization, the PALCE22V10 has preset and reset product terms. These terms are connected to all registered outputs. When the synchronous preset (SP) product term is asserted high, the output registers will be loaded with a HIGH on the next LOW-to-HIGH clock transition. When the asynchronous reset (AR) product term is asserted high, the output registers will be immediately loaded with a LOW independent of the clock ...

Page 5

... No special erase operation is required. Quality and Testability The PALCE22V10 offers a very high level of built-in quality. The erasability of the device provides a direct means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to provide the highest programming yields and post-programming functional yields in the industry ...

Page 6

... This saving is illustrated in the I Product-Term Disable On a programmed PALCE22V10Z, any product terms that are not used are disabled. Power is cut off from these product terms so that they do not draw current. As shown in the I graph, product-term disabling results in considerable power savings. This saving is greater at the higher frequencies ...

Page 7

... (13 GND 12 (14 PALCE22V10 and PALCE22V10Z Families 24 (28 I (27 I/O D ...

Page 8

... V OUT = Max (Note 2) V OUT = Max (Note 2) V OUT = 0 Max (Note 3) Outputs Open, (I OUT = 0 mA Max Outputs Open, (I OUT = 0 mA Max MHz CC PALCE22V10H-5 (Com’ with Min Max Unit 2.4 V ...

Page 9

... Test Conditions 2 OUT = 2.0 V Parameter Description LOW HIGH External Feedback 1/( Internal Feedback (f CNT ) 1/( (Note 4) No Feedback 1/( can be found using the following equation: CF PALCE22V10H-5 (Com’l) Typ Unit 5 25° MHz 1 -5 Min Max Unit ...

Page 10

... V OUT = Max (Note 2) V OUT = Max (Note 2) V OUT = 0.5 V, VCC = Max 25°C (Note 3) Outputs Open, (I OUT = 0 mA Max Outputs Open mA Max MHz OUT PALCE22V10H-7 (Com’ with CC Min Max Unit 2 ...

Page 11

... 5 25°C V OUT = 2 MHz PDIP Min 3.5 3.5 1/( 100 1/( (Note 4) 125 1/( 142.8 can be found using the following equation: CF PALCE22V10H-7 (Com’l) Typ Unit PLCC Max Min Max Unit 7.5 3 7 ...

Page 12

... Max (Note 2) V OUT = Max (Note 2) V OUT = Max (Note 2) V OUT = 0.5 V, VCC = Max 25°C (Note 3) Outputs Open , (I OUT = 0 mA Max MHz CC PALCE22V10H-10 (Com’ with CC Min Max Unit 2 ...

Page 13

... Test Conditions 2 OUT = 2.0 V Parameter Description LOW HIGH External Feedback 1/( Internal Feedback (f CNT ) 1/( (Note 3) No Feedback 1/( can be found using the following equation PALCE22V10H-10 (Com’l) Typ Unit 5 25° MHz -10 Min Max Unit 10 ns ...

Page 14

... (Note 2) V OUT = Max (Note 2) V OUT = 0 25°C (Note Outputs Open (I OUT V = Max (Note 4) CC and I (or I and I ). OZL IH OZH CC PALCE22V10Q-10 (Com’ with CC Min Max 2.4 0.4 2.0 0.8 10 -100 10 -100 -30 -130 = 0mA ...

Page 15

... Test Conditions 2 OUT = 2.0 V Parameter Description LOW HIGH External Feedback 1/( Internal Feedback (f CNT ) 1/( (Note 3) No Feedback 1/( can be found using the following equation: CF PALCE22V10Q-10 (Com’l) Typ Unit 5 25° MHz -10 Min Max Unit ...

Page 16

... V OUT = Max (Note 2) V OUT = Max (Note 2) V OUT = 0 25°C (Note Outputs Open mA Max OUT CC PALCE22V10H-15/25, Q-15/25 (Com’ with CC ) with CC Min Max Unit 2.4 V ...

Page 17

... 1/f (internal feedback MAX S Test Conditions 2 OUT = 2.0 V Min 1/( 1/( (Note 3) 58.8 can be found using the following equation: CF PALCE22V10H-15/25, Q-15/25 (Com’l) Typ Unit 5 25° MHz -15 -25 Max Min Max ...

Page 18

... Max (Note Max (Note 2) V OUT = 0 25°C (Note 3) H-20/ Outputs Open (I OUT = 0 mA Max H-10/ Outputs Open ( mA Max MHz OUT CC PALCE22V10H-10/15/20/25 (Ind with CC Min Max Unit 2.4 V 0.4 V 2.0 V ...

Page 19

... Min 1/( 83.3 50 110 58.8 1/( 125 83 can be found using the following equation: CF PALCE22V10H-10/15/20/25 (Ind) Typ Unit -15 -20 -25 Max Min Max Min Max Unit ...

Page 20

... V OUT = Max (Note 3) V OUT = Max (Note 3) V OUT = 0 Max (Note MHz Outputs Open (I OUT = 0 mA Max MHz PALCE22V10Z-15 (Ind -40°C to +85° with Min Max Unit 3 ...

Page 21

... CF MAX S Test Conditions 2 OUT = 2.0 V Parameter Description 1/( 1/( (Note 3) CNT S CF 1/( can be found using the following equation PALCE22V10Z-15 (Ind) Typ Unit 5 25° MHz 1 -15 Min Max 58.8 ) 62.5 15 ...

Page 22

... V OUT = Max (Note 3) V OUT = Max (Note 3) V OUT = 0 Max (Note MHz Outputs Open (I OUT = 0 mA Max MHz PALCE22V10Z-25 (Com’l, Ind 0°C to +75° with -40°C to +85°C A ...

Page 23

... LOW HIGH External Feedback 1/( Internal Feedback (f ) 1/( (Note CNT No Feedback 1/( can be found using the following equation: CF PALCE22V10Z-25 (Com’l, Ind) Typ Unit 5 25° MHz -25 Min Max Unit ...

Page 24

... T Clock Registered Output 16564-007 Input t WL Output 16564-009 d. Input to output disable/enable Input Asserting Synchronous V T Preset V Clock T t ARR Registered V Output T 16564-011 PALCE22V10 and PALCE22V10Z Families 16564-008 b. Registered output 0. 0.5V OL ...

Page 25

... Does Not Center Apply Line is High- Impedance “Off” State Test Point 300 5 pF PALCE22V10 and PALCE22V10Z Families 16564E-013 16564-014 Commercial Measured Output R Value 2 1.5 V All except H-5/7: 390 1.5 V H-5/ 300 0 0 ...

Page 26

... By utilizing 50% of the device, a midpoint is defined for I down to estimate the I requirements for a particular design Frequency (MHz vs. Frequency ., From this midpoint, a designer may scale the I CC PALCE22V10 and PALCE22V10Z Families 22V10H-5 22V10H-7 22V10H-10 22V10H-15 22V10H-25 22V10Q-10 22V10Q- 16564E-015 ...

Page 27

... TYPICAL I CHARACTERISTICS FOR THE PALCE22V10Z- 5 25° 120 100 (mA *Percent of product terms used. I vs. Frequency Graph for the PALCE22V10Z- Frequency (MHz Frequency (MHz) PALCE22V10 and PALCE22V10Z Families 100%* 50%* 25 ...

Page 28

... ENDURANCE CHARACTERISTICS The PALCE22V10 is manufactured using Vantis’ advanced electrically-erasable (EE) CMOS process. This technology uses an EE cell to replace the fuse link used in bipolar parts result, the device can be erased and reprogrammed—a feature which allows 100% testing at the factory. Symbol ...

Page 29

... ROBUSTNESS FEATURES The PALCE22V10X-X/5 devices have some unique features that make them extremely robust, especially when operating in high-speed design environments. Pull-up resistors on inputs and I/O pins cause unconnected pins to default to a known state. Input clamping circuitry limits negative overshoot, eliminating the possibility of false clocking caused by subsequent ringing. A special noise fi ...

Page 30

... INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR PALCE22V10Z ESD Input Protection Transition and Detection Clamping Programming Pins only Programming Voltage Detection Typical Input V CC Provides ESD Protection and Clamping Preload Circuitry Typical Output PALCE22V10 and PALCE22V10Z Families Positive Programming Overshoot Circuitry Filter Feedback ...

Page 31

... Power-up Reset Time PR t Input or Feedback Setup Time S t Clock Width LOW Power Registered Active-Low Output Clock V CC Off Figure 3. Power-Up Reset Waveform PALCE22V10 and PALCE22V10Z Families can rise CC Max Unit 1000 ns See Switching Characteristics V CC 16564E-021 31 ...

Page 32

... Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant tem- perature. Therefore, the measurements can only be used in a similar environment. 32 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air PALCE22V10 and PALCE22V10Z Families Typ SKINNY DIP PLCC Unit 20 18 ° ...

Page 33

... Supply Voltage 16564E-002 PALCE22V10 and PALCE22V10Z Families PLCC GND I/O 2 16564E-003 33 ...

Page 34

... Valid Combinations list configurations planned supported in volume for this device. Consult the local Lattice/Vantis sales office to confirm availability of /4 specific valid combinations and to check on newly released combinations. PALCE22V10 and PALCE22V10Z Families PROGRAMMING DESIGNATOR Blank = Initial Algorithm /4 = First Revision /5 = Second Revision ...

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