USB3300_06 SMSC [SMSC Corporation], USB3300_06 Datasheet
USB3300_06
Related parts for USB3300_06
USB3300_06 Summary of contents
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PRODUCT FEATURES USB-IF Hi-Speed certified to the Universal Serial Bus Specification Rev 2.0 Interface compliant with the ULPI Specification revision 1.1 in 8-bit mode Industry standard UTMI+ Low Pin Interface (ULPI) Converts 54 UTMI+ signals into a standard 12 pin ...
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USB3300-EZK FOR 32 PIN, QFN PACKAGE (GREEN, LEAD-FREE) 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2006 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet 0.1 Reference Documents Universal Serial Bus Specification, Revision 2.0, April 27, 2000 On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a, June 24, 2003 USB 2.0 Transceiver ...
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Table of Contents 0.1 Reference Documents ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet List of Figures Figure 1.1 Basic ULPI USB Device Block Diagram ...
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List of Tables Table 3.1 USB3300 Pin Definitions 32-Pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Chapter 1 General Description The USB3300 is an industrial temperature Hi-Speed USB Physical Layer Transceiver (PHY). The USB3300 uses a low pin count interface (ULPI) to connect ...
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Hi-Speed Peripheral, host controllers, On-the- Hi-Speed Peripheral, host controllers, On- Hi-Speed Peripheral, host controllers, On- (HS, FS, and LS but no preamble packet) Hi-Speed Peripheral, host controllers, Figure 1.2 ULPI Interface Features as Related to UTMI+ Revision 1.06 (07-19-06) Hi-Speed ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Chapter 2 Functional Overview The USB3300 is a highly integrated USB PHY. It contains a complete Hi-Speed USB2.0 PHY with the ULPI industry standard interface to support ...
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Chapter 3 Pin Layout The USB3300 is offered pin QFN package ( 0.9mm). The pin definitions and locations are documented below. 3.1 USB3300 Pin Diagram GND GND CPEN VBUS ID VDD3 Figure ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Table 3.1 USB3300 Pin Definitions 32-Pin QFN Package (continued) DIRECTION, PIN NAME 4 VBUS VDD3 Input, CMOS 9 RESET Input, ...
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Table 3.1 USB3300 Pin Definitions 32-Pin QFN Package (continued) DIRECTION, PIN NAME 17 DATA[7] 18 DATA[6] 19 DATA[5] 20 DATA[4] 21 DATA[3] 22 DATA[2] 23 DATA[1] 24 DATA[0] 25 VDD3.3 26 VDD1 VDDA1.8 30 VDD3.3 ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Table 3.1 USB3300 Pin Definitions 32-Pin QFN Package (continued) DIRECTION, PIN NAME 31 REG_EN 32 RBIAS GND FLAG SMSC USB3300 ACTIVE TYPE LEVEL DESCRIPTION I/O, N/A On ...
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Chapter 4 Operational Description PARAMETER SYMBOL Maximum VBUS, ID, V MAX_5V EXTVBUS, DP, and DM voltage to GND Maximum VDD1.8 and V MAX_1.8V VDDA1.8 voltage to Ground Maximum 3.3V supply V MAX_3.3V voltage to Ground Maximum I/O voltage to V ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Chapter 5 Electrical Characteristics Table 5.1 Electrical Characteristics: Supply Pins PARAMETER Unconfigured Current FS Idle 3.3V Current FS Idle 1.8V Current FS Transmit 3.3V Current FS Transmit ...
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Table 5.3 DC Electrical Characteristics: Logic Pins PARAMETER SYMBOL Low-Level Input Voltage V IL High-Level Input Voltage V IH Low-Level Output Voltage V OL High-Level Output Voltage V OH Input Leakage Current I LI Pin Capacitance Cpin Note ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Table 5.4 DC Electrical Characteristics: Analog I/O Pins (DP/DM) (continued) PARAMETER SYMBOL HS FUNCTIONALITY Input levels HS Differential Input V DIHS Sensitivity HS Data Signaling Common V ...
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Table 5.5 Dynamic Characteristics: Analog I/O Pins (DP/DM) (continued) PARAMETER SYMBOL Differential Rise/Fall Time FRFM Matching HS Output Driver Timing Differential Rise Time T HSR Differential Fall Time T HSF Driver Waveform Requirements Hi-Speed Mode Timing Receiver Waveform Requirements Data ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Chapter 6 Architecture Overview The USB3300 architecture can be broken down into the following blocks shown in Internal VDD3.3 Regulator & POR DATA[7:0] CLKOUT STP ULPI Digital ...
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The advantage of a “wrapper less” architecture is that the PHY has a lower USB latency than a design which must first register signals into the PHY’s wrapper before the transfer to the PHY core. A low latency PHY allows ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet 6.1.2 ULPI Interface Signals UTMI+ Low Pin Interface (ULPI) uses 12-pins to connect a full OTG Host / Device PHY to an SOC. A reduction of external ...
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ULPI Interface Timing The control and data timing relationships are given in provides CLKOUT and all timing is relative to the rising clock edge. The timing relationships detailed below apply to Synchronous Mode only. Clock Out - CLKOUT T ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet REGISTER NAME Vendor ID Low Vendor ID High Product ID Low Product ID High Function Control Interface Control OTG Control USB Interrupt Enable Rising USB Interrupt Enable ...
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Product ID Low: Address = 02h (read only) FIELD NAME BIT Product ID Low 7:0 6.1.4.4 Vendor ID Low: Address = 03h (read only) FIELD NAME BIT Product ID High 7:0 6.1.4.5 Function Control: Address = 04-06h (read), 04h ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet 6.1.4.6 Interface Control: Address = 07-09h (read), 07h (write), 08h (set), 09h (clear) FIELD NAME BIT 6-pin FsLsSerialMode 0 3-pin FsLsSerialMode 1 Reserved 2 ClockSuspendM 3 AutoResume ...
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FIELD NAME BIT DrvVbus 5 DrvVbusExternal 6 UseExternalVbus 7 Indicator 6.1.4.8 USB Interrupt Enable Rising: Address = 0D-0Fh (read), 0Dh (write), 0Eh (set), 0Fh (clear) FIELD NAME BIT HostDisconnect Rise 0 VbusValid Rise 1 SessValid Rise 2 SessEnd Rise 3 ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet FIELD NAME BIT SessEnd Fall 3 IdGnd Fall 4 Reserved 7:5 6.1.4.10 USB Interrupt Status Register: Address = 13h (read only with auto clear) FIELD NAME BIT ...
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Debug Register: Address = 15h (read only) FIELD NAME BIT Linestate0 0 Linestate1 1 Reserved 7:2 6.1.4.13 Scratch Register: Address = 16-18h (read), 16h (write), 17h (set), 18h (clear) FIELD NAME BIT Scratch 7:0 6.1.4.14 Carkit Register Access The ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Table 6.4 ULPI TXD CMD Byte Encoding (continued) CMD COMMAND NAME BITS[7:6] Register Write 10b Register Read 11b 6.1.5.1 ULPI Register Write A ULPI register write operation ...
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ULPI Register Read A ULPI register read operation is given in = 11h for a register read. DATA[5:0] of the ULPI TXD command bye contain the register address. T0 CLK DATA[7:0] Idle DIR STP NXT At T0, the Link ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet during a USB receive when NXT is low. after STP is asserted during a USB transmit cmd. DATA[7:0] NAME DESCRIPTION AND VALUE [1:0] Linestate UTMI Linestate Signals ...
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The USB3300 transmitter will transmit a 32-bit long high speed synch before every high speed packet. In full and low speed modes a 8-bit synch is transmitted. When the device or host needs to chirp for high speed port negotiation, ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet CLK DATA[7:0] TXD CM D Idle (USB tx) DIR NXT STP DP/DM SE0 During transmit the PHY will use NXT to control the rate of data flow ...
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CLK DATA[7:0] Turn Idle around DIR STP NXT In Figure 6.7 the PHY asserts DIR to take control of the data bus from the Link. The assertion of DIR and NXT in the same cycle contains additional information that Rxactive ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet T0 T1 CLK DATA[7:0] Idle DIR STP NXT SUSPENDM (ULPI Register Bit) While in Low Power Mode, the Data interface is redefined so that the Link can ...
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Synchronous Mode. The PHY will automatically set the SuspendM bit the Function Control register. T0 CLK DATA[7:0] LOW POWER MODE DIR STP Note: Not to Scale NXT The time from ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet A Link design which drives STP high during POR can disable the pull-up resistor on STP by setting InterfaceProtectDisable bit motivation for this is ...
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FS/LS Serial Mode Three pin serial mode utilizes the data bus pins for the serial functions shown in Table 6.7 Pin Definitions in 3 pin Serial Mode CONNECTED SIGNAL TO tx_enable DATA[0] data DATA[1] se0 DATA[2] interrupt DATA[3] ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet RPU_DP_EN activates the 1.5kΩ DP pull-up resistor RPU_DM_EN activates the 1.5kΩ DM pull-up resistor RPD_DP_EN activates the 15kΩ DP pull-down resistor RPD_DM_EN activates the 15kΩ DM pull-down ...
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Table 6.8 DP/DM termination vs. Signaling Mode (continued) SIGNALING MODE OTG device, Peripheral Chirp OTG device, Peripheral HS OTG device, Peripheral FS OTG device, Peripheral HS/FS Suspend OTG device, Peripheral HS/FS Resume OTG device, Peripheral Test J/Test K Note: This ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet 6.4.1 Internal Regulators The USB3300 has two internal regulators that create two 1.8V outputs (labeled VDD1.8 and VDDA1.8) from the 3.3volt power supply input (VDD3.3). Each regulator ...
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ID VDD33 VBUS EXTVBUS IndicatorComplement [UseExternalVbusindicator, IndicatorPassThru] CPEN The OTG Module can be broken into 4 main blocks; ID Detection, VBUS Control, Driving External Vbus, and External Vbus Detection. Each of these blocks is covered in the sections below. 6.5.1 ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet be overpowered and the ID pin will be brought to ground. To save current when a Mini-A Plug is inserted, the ID pull-up resistor can be disabled ...
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Vbus Pull-up and Pull-down Resistors In addition to the internal Vbus comparators the USB3300 also includes the integrated Vbus pull-up and pull-down resistors used for Vbus Pulsing. To discharge the Vbus voltage, so that a Session Request can begin, ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Table 6.10 External Vbus Indicator Logic (continued) USE EXTERNAL TYPICAL VBUS APPLICATION INDICATOR Standard Host 1 1 Standard 0 Peripheral SMSC does not recommend using the ExternalVbus ...
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Chapter 7 Application Notes 7.1 Application Diagram VDD3.3 3.3 Volt Supply C Min Max VBUS Host 100uF Device 1uF 10uF OTG Device 1uF 6.5uF USB Connector (Standard or Mini) C VBUS 5 Volt Supply Fault Host Only Figure 7.1 USB3300 ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet DIR DIR NXT NXT STP STP CLOCK CLOCK DATA[7] DATA[7] DATA[6] DATA[6] DATA[5] DATA[5] DATA[4] DATA[4] DATA[3] DATA[3] DATA[2] DATA[2] DATA[1] DATA[1] DATA[0] DATA[0] SOC w/ ULPI ...
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IEC61000-4-2 Performance The IEC61000-4-2 ESD specification is an international standard that addresses system-level immunity to ESD strikes while the end equipment is operational. In contrast, the HBM ESD tests are performed at the device level with the device powered ...
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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Chapter 8 Package Outline The USB3300 is offered in a compact 32 pin lead-free QFN package. Figure 8.1 USB3300-EZK 32 Pin QFN Package Outline ...