P82B96T PHILIPS [NXP Semiconductors], P82B96T Datasheet - Page 5

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P82B96T

Manufacturer Part Number
P82B96T
Description
Dual bidirectional bus buffer
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet

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NXP Semiconductors
8. Limiting values
P82B96_6
Product data sheet
special ‘buffered LOW’ is applied to the Sx/Sy of another P82B96 that second P82B96 will
not recognize it as a ‘regular I
The Sx/Sy side of P82B96 may not be connected to similar buffers that rely on special
logic thresholds for their operation, for example PCA9511, PCA9515, or PCA9518. The
Sx/Sy side is only intended for, and compatible with, the normal I
levels of I
required. The Tx/Rx and Ty/Ry I/O pins use the standard I
I
pins to other P82B96s, for example in a star or multipoint configuration with the Tx/Rx and
Ty/Ry I/O pins on the common bus and the Sx/Sy side connected to the line card slave
devices. For more details see Application Note AN255 .
Table 4.
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages with respect to pin GND.
Symbol
V
V
V
V
I
P
T
T
T
2
n
C-bus parts. There are no restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O
j
stg
amb
CC
Sx
Tx
Rx
tot
2
C-bus master and slave chips, or even Tx/Rx signals of a second P82B96 if
Limiting values
Parameter
supply voltage
voltage on pin Sx
voltage on pin Tx
voltage on pin Rx
current on any pin
total power dissipation
junction temperature
storage temperature
ambient temperature
Rev. 06 — 31 January 2008
2
C-bus LOW’ and will not propagate it to its Tx/Ty output.
Conditions
V
I
buffered output
receive input
operating range
P82B96TD/S410
operating
2
CC
C-bus SDA or SCL
to GND
2
C-bus logic voltage levels of all
Dual bidirectional bus buffer
Min
-
-
2
0.3
0.3
0.3
0.3
40
55
40
C-bus logic voltage
© NXP B.V. 2008. All rights reserved.
P82B96
Max
+18
+18
+18
+18
250
300
+125
+125
+85
Unit
V
V
V
V
mA
mW
C
C
C
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