HCTL-2000_06 AVAGO [AVAGO TECHNOLOGIES LIMITED], HCTL-2000_06 Datasheet - Page 18

• Manufacturer Part Number: HCTL-2000_06
• Description: Quadrature Decoder/Counter Interface ICs
• Manufacturer: AVAGO [AVAGO TECHNOLOGIES LIMITED]

18
Figure 19. 8748 READ Cycle from Figure 18.
Actions
1. ANL P1, 00H has just been
2. The HCTL-20XX detects that
3. INS A, BUS has just been
4. ORL PORT 1, 02H has just
executed. The output of bits 0
and 1 of Port 1 cause SEL and
OE to be logic low. The data
lines output the higher order
byte.
OE and SEL are low on the
next falling edge of the CLK
and asserts the internal inhibit
signal. Data can be read
without regard for the phase of
the CLK.
executed. Data is read into the
8748.
been executed. The program
sets SEL high and leaves OE
low by writing the correct
values to port 1. The HCTL-
ANL P1, OOH
5. INS A, BUS has just been
6. ORL P1, 03H has just been
20XX detects OE is low and
SEL is high on the next falling
edge of the CLK, and thus the
first inhibit reset condition is
met.
executed. Lower order data
bits are read into the 8748.
executed. The HCTL-20XX
detects OE high on the next
falling edge of CLK. The
program sets OE and SEL high
by writing the correct values to
port 1. This causes the data
lines to be tristated. This
satisfies the second inhibit and
reset condition. On the next
rising CLK edge new data is
transferred from the counter to
the position data latch.
ORL P1, 02H
Additional Information from Avago
Technologies
Application briefs are available
from the factory. Please contact
your local Avago sales
representative for the following.
M027 Interfacing the HCTL-20XX
M019 Commonly Asked
M020 A Simple Interface for the
M023 Interfacing the MC68HCII
to the 8051
Questions about the HCTL-
2020 and Answers
HCTL-2020 with a 16-bit
DAC without Using a
Processor
to the HCTL-2020