HCTL-2017-A00 Avago Technologies US Inc., HCTL-2017-A00 Datasheet
HCTL-2017-A00
Specifications of HCTL-2017-A00
HCTL-2017-A00
Available stocks
Related parts for HCTL-2017-A00
HCTL-2017-A00 Summary of contents
Page 1
... The use of Schmitt-triggered CMOS inputs and input noise filters allows reliable operation in noisy environments. The HCTL-2001-A00 contains 12-bit counter and HCTL-2017-A00/PLC or HCTL-2021- A00/PLC contains 16-bit counter and provides TLL/ CMOS compatible tri-state output buffers. Operation is specified for a temperature range from –40 to +85°C at clock frequencies up to 14MHz ...
Page 2
Devices PINOUT VDD 2 CLK D1 3 SEL RST VSS D7 PINOUT C Package Dimensions (dimension in mm) See Appendix A. 2 ...
Page 3
Operating Characteristics Table 1. Absolute Maximum Ratings (All voltages below are referenced to V Parameter Symbol DC Supply Voltage V Input Voltage V Storage Temperature T [1] Operating Temperature T Table 2. Recommended Operating Conditions Parameter Symbol DC Supply Voltage ...
Page 4
... CNTCAS outputs. The proper signal U (high level (low level) will be present before the rising edge of the CNTDCDR and CNTCAS outputs. A pulse is presented on this LSTTL-compatible output when the HCTL-2021- A00 internal counter overflows or underflows. The rising edge on this waveform may be used to trigger an external counter. ...
Page 5
... The proper signal U (high level (low level) will be present before the rising edge of the CNTDCDR and CNTCAS outputs. CNTCAS pulse is presented on this LSTTL-compatible output when the HCTL-2021-PLC internal counter overflows or underflows. The rising edge on this waveform may be used to trigger an external counter ...
Page 6
Switching Characteristics Table 5. Switching Characteristics Max/Min specifications at V Symbol Description 1 tCLK Clock Period 2 tCHH Pulse width, clock high 3 tCD Delay time, rising edge of clock to valid, updated count information on D0-7 4 tODE Delay ...
Page 7
Figure 3: Tri-State Output Timing Figure 4: Bus Control Timing Figure 5: Decoder, Cascade Output Timing 7 ...
Page 8
Figure 6. Simplified Logic Diagram Digital Noise Filter The digital noise filter section is responsible for rejecting noise on the incoming quadrature signals. The input section uses two techniques to implement improved noise rejection. Schmitt-trigger inputs and a three-clock-cycle delay ...
Page 9
CHA CHB Figure 7. Simplified Digital Noise Filter Logic 3 t CLK CLK CHA CHB Noise Spike CHA filtered CHB filtered CHI filtered Figure 8. Signal ...
Page 10
... Two’s-complement arithmetic is normally used to compute position from these periodic position updates. D. The system count is >16 bits so the HCTL-2021- A00/PLC can be cascaded with other standard counter ICs to give absolute position. - low or high) has to be greater than E ) ...
Page 11
... Quadrature Decoder Output The quadrature decoder output section consists of count and up/down outputs derived from the 4x decoder mode of the HCTL-2021-A00/PLC. When the decoder has detected a count, a pulse, one-half clock cycle long, will be output on the CNT output will occur during the clock cycle in which the internal counter is updated ...
Page 12
... A count occurring in the HCTL-2021- A00/PLC will cause the counter to roll over and a cascade pulse will be generated. A read starting on this clock cycle will show FFFFh from the HCTL-2021- A00/PLC. The external latch should read F0h, but if the host latches the count after the cascade signal ...
Page 13
... For proper operation of the inhibit logic during a two- byte read, OE and SEL must be synchronous with CLK due to the falling edge sampling of OE and SEL. The internal inhibit logic on the HCTL-2021-A00/PLC inhibits the transfer of data from the counter to the position data latch during the time that the latch outputs are being read ...
Page 14
APPENDIX A PACKAGE A PIN 1 IDENT PIN # SECTION A-A 14 OPTIONAL EJECTOR PIN INDENTION SHOWN FOR CONVENTIONAL MOLD ONLY BASE PLANE SEATING PLANE SYMBOL MIN. NOM. MAX ...
Page 15
PACKAGE B OPTIONAL EJECTOR PIN INDENTION SHOWN L C PIN #1 PIN 1 IDENT SECTION A-A 15 FOR CONVENTIONAL MOLD ONLY BASE PLANE SEATING PLANE SYMBOL MIN. NOM. MAX .175 ...
Page 16
PACKAGE C TOP VIEW B1 e D2/E2 SIDE VIEW For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United ...