HCTL-2017-A00 Avago Technologies US Inc., HCTL-2017-A00 Datasheet - Page 4

• Manufacturer Part Number: HCTL-2017-A00
• Description: IC DECODER/COUNTER 16BIT 16-DIP
• Manufacturer: Avago Technologies US Inc.

Specifications of HCTL-2017-A00

• Package / Case: 16-DIP (0.300", 7.62mm)
• Applications: Encoder to Microprocessor
• Interface: 8-Bit Tristate
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Through Hole
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 516-1881-5; HCTL-2017-A00

Functional Pin Description
Table 4a. Functional Pin Descriptions (PDIP Package)
4
RST
U/D
D0
D1
D2
D3
D4
D5
D6
D7
NC
Symbol
VDD
VSS
CLK
CHA
CHB
OE
SEL
CNT
CNTCAS NA
DCDR
Pin
HCTL-
2001-
16
2
NA
NA
1
15
14
13
12
11
10
NA
A00
8
7 6
5
4
3
9
HCTL-
16
NA
NA
NA
1
15
14
13
12
11
10
NA
2017-
8
2
7 6
5
4
3
9
A00
HCTL-
10
16
15
1
19
18
17
14
13
12
11
2021-
20
2
9 8
7
4
3
5
6
A00
Description
Power Supply
Ground
CLK is a Schmitt-trigger input for the external clock signal.
CHA and CHB are Schmitt-trigger inputs that accept the outputs from a
respect to any other input signals.
is enabled into the 8-bit tri-state output buffer. As in OE/ above, SEL also
is counting up or down and is intended to be used with the CNTDCDR and
CNTCAS outputs. The proper signal U (high level) or D/ (low level) will be
present before the rising edge of the CNTDCDR and CNTCAS outputs.
bytes. The High byte is read first followed by the Low bytes.
Not connected - this pin should be left floating.
quadrature-encoded source, such as incremental optical shaft encoder. Two
channels, A and B, nominally 90 degrees out of phase, are required.
This active low Schmitt-trigger input clears the internal position counter and
This CMOS active low input enables the tri-state output buffers. The OE/
and SEL inputs are sampled by the internal inhibit logic on the falling edge
of the clock to control the loading of the internal position data latch.
These CMOS inputs directly controls which data byte from the position latch
control the internal inhibit logic.
A pulse is presented on this LSTTL-compatible output when the quadrature
decoder has detected a state transition. CNT
This LSTTL-compatible output allows the user to determine whether the IC
A pulse is presented on this LSTTL-compatible output when the HCTL-2021-
A00 internal counter overflows or underflows. The rising edge on this
These LSTTL-compatible tri-state outputs form an 8-bit output ports through
the position latch. It also resets the inhibit logic. RST is asynchronous with
waveform may be used to trigger an external counter.
which the contents of the 16-bit position latch may be read in 2 sequential
SEL
0
1
BYTE SELECTED
High
Low