HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 278

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HD6412373R

Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 6 Bus Controller (BSC)
Depending on the DRAM used, modification of the WE signal may not be permitted during the
refresh period. In this case, the CBRM bit in REFCR should be set to 1. The bus controller will
then insert refresh cycles in appropriate breaks between bus cycles. Figure 6.38 shows an example
of the timing when the CBRM bit is set to 1. In this case the CS signal is not controlled, and
retains its value prior to the start of the refresh period.
Rev.7.00 Mar. 18, 2009 page 210 of 1136
REJ09B0109-0700
φ
CSn (RASn)
UCAS, LCAS
(RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0)
T
Rp
Figure 6.37 CBR Refresh Timing
T
Rrw
T
Rr
T
Rc1
T
Rc2

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