HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 850

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HD6412373R

Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 16 I
16.3.5
ICSR is an 8-bit readable/writable register that performs confirmation of interrupt request flags
and status.
Bit
7
6
5
Rev.7.00 Mar. 18, 2009 page 782 of 1136
REJ09B0109-0700
Bit Name
TDRE
TEND
RDRF
I
2
C Bus Status Register (ICSR)
2
C Bus Interface 2 (IIC2) (Option)
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Transmit Data Register Empty
[Setting condition]
[Clearing conditions]
Transmit end
[Setting conditions]
[Clearing conditions]
[Setting condition]
[Clearing conditions]
Description
Receive Data Register Full
When data is transferred from ICDRT to ICDRS
and ICDRT becomes empty
When TRS has been set
When a transition from the receive mode to the
transmit mode has been made in the slave mode
When 0 is written in TDRE after reading TDRE = 1
When data is written in ICDRT
When the ninth clock of SCL is rose while the
TDRE flag is 1
When 0 is written in TEND after reading TEND = 1
When data is written in ICDRT
When a received data is transferred from ICDRS
to ICDRR
When 0 is written in RDRF after reading RDRF =
1
When data is read from ICDRR

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