HD6417606 RENESAS [Renesas Technology Corp], HD6417606 Datasheet - Page 327

• Manufacturer Part Number: HD6417606
• Manufacturer: RENESAS [Renesas Technology Corp]

This LSI incorporates a host interface (HIF) for use in high-speed transfer of data between
external devices which cannot utilize the system bus.
The HIF allows external devices to read from and write to 2 kbytes (1 kbyte × 2 banks) of the on-
chip RAM exclusively for HIF use (HIFRAM) within this LSI, in 32-bit units. Interrupts issued to
this LSI by an external device, interrupts sent from this LSI to the external device, and DMA
transfer requests sent from this LSI to the external device are also supported. By using HIFRAM
and these interrupt functions, software-based data transfer between external devices and this LSI
becomes possible, and connection to external devices not releasing bus mastership is enabled.
Using HIFRAM, the HIF also supports HIF boot mode allowing this LSI to be booted.
13.1
The HIF has the following features.
• An external device can read from or write to HIFRAM in 32-bit units via the HIF pins (access
• When an external device accesses HIFRAM via the HIF pins, automatic increment of
• By writing to specific bits in the HIF internal registers from an external device, or by accessing
• There are seven interrupt source bits each for internal interrupts and external interrupts.
• In HIF boot mode, this LSI can be booted from HIFRAM by an external device storing the
in 8-bit or 16-bit units not allowed). The on-chip CPU can read from or write to HIFRAM in 8-
bit, 16-bit, or 32-bit units, via the internal peripheral bus. The HIFRAM access mode can be
specified as bank mode or non-bank mode.
addresses and the endian can be specified with the HIF internal registers.
the end address of HIFRAM from the external device, interrupts (internal interrupts) can be
issued to the on-chip CPU. Conversely, by writing to specific bits in the HIF internal registers
from the on-chip CPU, interrupts (external interrupts) or DMAC transfer requests can be sent
from the on-chip CPU to the external device.
Accordingly, software control of 128 different interrupts is possible, enabling high-speed data
transfer using interrupts.
instruction code in HIFRAM.
Features
Section 13 Host Interface (HIF)
Rev. 4.00 Sep. 13, 2007 Page 301 of 502
Section 13 Host Interface (HIF)
REJ09B0239-0400