74ALVCF322835_04 FAIRCHILD [Fairchild Semiconductor], 74ALVCF322835_04 Datasheet

74ALVCF322835_04

Manufacturer Part Number

74ALVCF322835_04

Description

Low Voltage 36-Bit Universal Bus Driver with 3.6V Tolerant Outputs and 26ohm Series Resistors in Outputs

Manufacturer

FAIRCHILD [Fairchild Semiconductor]

Datasheet

1.74ALVCF322835_04.pdf (7 pages)

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74ALVCF322835G

(Note 1)(Note 2)

74ALVCF322835

Low Voltage 36-Bit Universal Bus Driver

with 3.6V Tolerant Outputs

and 26 Series Resistors in Outputs

General Description

The 74ALVCF322835 low voltage 36-bit universal bus

driver combines D-type latches and D-type flip-flops to

allow data flow in transparent, latched and clocked modes.

Data flow is controlled by output-enable (OE), latch-enable

(LE), and clock (CLK) inputs. The device operates in

Transparent Mode when LE is held HIGH. The device

operates in clocked mode when LE is LOW and CLK is tog-

gled. Data transfers from the Inputs (I

a Positive Edge Transition of the Clock. When OE is LOW,

the output data is enabled. When OE is HIGH the output

port is in a high impedance state.

The 74ALVCF322835 is designed with 26 series resistors

in the outputs. This design reduces noise in applications

such as memory address drivers, clock drivers, and bus

transceivers/transmitters.

The 74ALVCF322835 is designed for low voltage (1.65V to

3.6V) V

The 74ALVCF322835 is fabricated with an advanced

CMOS technology to achieve high speed operation while

maintaining low CMOS power dissipation.

Ordering Code:

Note 1: Ordering Code “G” indicates Trays.

Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Order Number

applications with I/O capability up to 3.6V.

BGA114A

Package

Number

) to Outputs (O

114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

DS500741

) on

Features

Compatible with PC133 DIMM module specifications

1.65V to 3.6V V

3.6V tolerant outputs

26 series resistors in outputs

Power-down high impedance outputs

Latchup conforms to JEDEC JED78

ESD performance:

3.7 ns max for 3.0V to 3.6V V

4.6 ns max for 2.3V to 2.7V V

7.4 ns max for 1.65V to 1.95V V

Human body model

Machine model 200V

(CLK to O

Package Description

)

specifications provided

2000V

May 2002

Revised November 2004

www.fairchildsemi.com

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74ALVCF322835_04 Summary of contents

Page 1

Low Voltage 36-Bit Universal Bus Driver with 3.6V Tolerant Outputs and 26 Series Resistors in Outputs General Description The 74ALVCF322835 low voltage 36-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched ...

Page 2

Connection Diagram (Top Thru View) Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW Latch Enable Input n CLK Clock Input Data Inputs Data Inputs 1 18 ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 6) 0. Input Diode Current ( Output Diode Current (I ) ...

Page 4

AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX Propagation Delay PHL PLH Bus-to-Bus Propagation Delay PHL PLH Clock to Bus Propagation Delay PHL PLH LE to Bus t , ...

Page 5

Characteristics OUT OUT FIGURE 1. Characteristics for Output - Pull Up Drive FIGURE 2. Characteristics for Output - Pull Down Driver I versus versus www.fairchildsemi.com ...

Page 6

AC Loading and Waveforms FIGURE 3. AC Test Circuit (Input Characteristics 1MHz; t Symbol 3.3V 0. FIGURE 4. Waveform ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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