AT88SA100S-SH-CZ-T ATMEL [ATMEL Corporation], AT88SA100S-SH-CZ-T Datasheet - Page 10

• Manufacturer Part Number: AT88SA100S-SH-CZ-T
• Description: Atmel CryptoAuthentication Battery Authentication Chip
• Manufacturer: ATMEL [ATMEL Corporation]

5.1.4
5.2
5.3
To achieve the specified I
achieve I
additional leakage on the input circuit of the chip.
Pause State
The pause state is entered via the PauseLong command and can be exited only when the watchdog timer has expired and the
chip transitions to a sleep state. When in the pause state, the chip ignores all transitions on the signal pin but does not enter a
low power consumption mode.
The pause state provides a mechanism for multiple AT88SA100S chips on the same wire to be selected and to exchange data
with the host microprocessor. The PauseLong command includes an optional address field which is compared to the values in
Fuses 84-87. If the two matches, then the chip enters the pause state, otherwise, it continues to monitor the bus for
subsequent commands. The host would selectively put all but one AT88SA100S in the pause state before executing the MAC
command on the active chip. After the end of the watchdog interval all the chips will have entered the sleep state and the
selection process can be started with a Wake token (which will then be honored by all chips) and selection of a subsequent
chip.
IO Blocks
Commands are sent to the chip, and responses received from the chip, within a block that is constructed in the following way:
IO Flow
The general IO flow for a MAC command is as follows:
All commands other than MAC have a short execution delay. In these cases the system should omit steps six, seven, and
eight and replace this with a wait of duration t
Byte Number Name
0
1 to (N-2)
N-1, N
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Receive output block from the AT88SA100S, system checks CRC
11. If CRC from the AT88SA100S is incorrect, indicating a transmission error, system resends transmit flag
12. System sends sleep flag to the AT88SA100S
System sends wake token
System sends transmit flag
Receive 0x11 value from the AT88SA100S to verify proper wakeup synchronization
System sends command flag
System sends command block
System waits t
System sends transmit flag. If command format is OK, the AT88SA100S ignores this flag because the computation
System waits t
System sends transmit flag
engine is busy. If there was an error, the AT88SA100S responds with an error code
SLEEP
if the sleep state of the input pin is high, the voltage on the input signal should be within 0.3V of V
Count
Packet
Checksum CRC-16 verification of the count and packet bytes. The CRC polynomial is 0x8005, the initial
PARSE
EXEC
SLEEP
. See Section 5.1.1
for the AT88SA100S to check for command formation errors
Meaning
Number of bytes to be transferred to the chip in the block, including count, packet and checksum,
so this byte should always have a value of (N+1). The maximum size block is 39 and the
minimum size block is four. Values outside this range will cause unpredictable operation.
Command, parameters and data, or response
See Section 6 for more details
register value should be zero and after the last bit of the count and packet have been transmitted
the internal CRC register should have a value that matches that in the block. The first byte
transmitted (N-1) is the least significant byte of the CRC value so the last byte of the block is the
most significant byte of the CRC.
, Atmel recommends that the input signal be brought below V
PARSE
+ t
EXEC
.
Atmel AT88SA100S [DATASHEET]
IL
when the chip is asleep. To
8558F−CRYPTO−9/11
CC
to avoid
10