AT25128A-W1.8-11 ATMEL [ATMEL Corporation], AT25128A-W1.8-11 Datasheet

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AT25128A-W1.8-11

Manufacturer Part Number
AT25128A-W1.8-11
Description
SPI Serial EEPROMs
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
Features
Description
The AT25128A/256A provides 131,072/262,144 bits of serial electrically-erasable
programmable read only memory (EEPROM) organized as 16,384/32,768 words of
8 bits each. The device is optimized for use in many industrial and commercial appli-
cations where low-power and low-voltage operation are essential. The devices are
available in space saving 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-
lead TSSOP, 8-ball dBGA2 and 8-lead SAP packages. In addition, the entire family is
available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
The AT25128A/256A is enabled through the Chip Select pin (CS) and accessed via
a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate Erase cycle is required before Write.
Table 1. Pin Configurations
Pin Name
CS
SCK
SI
SO
GND
VCC
WP
HOLD
NC
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
Data Sheet Describes Mode 0 Operation
Low-voltage and Standard-voltage Operation
20 MHz Clock Rate (5V)
64-byte Page Mode and Byte Write Operation
Block Write Protection
Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
Self-timed Write Cycle (5 ms Max)
High-reliability
Automotive Grade, Extended Temperature and Lead-free/Halogen-free
Devices Available
8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-ball dBGA2 and
8-lead SAP Packages
Die Sales: Wafer Form, Waffle Pack, and Bumped Die
– 2.7 (V
– 1.8 (V
– Protect 1/4, 1/2, or Entire Array
– Endurance: 1 Million Write Cycles
– Data Retention: >100 Years
CC
CC
= 2.7V to 5.5V)
= 1.8V to 5.5V)
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Write Protect
Suspends Serial Input
No Connect
GND
GND
WP
SO
WP
CS
SO
CS
8-lead TSSOP
8-lead PDIP
1
2
3
4
1
2
3
4
HOLD
8
7
6
5
8
7
6
5
VCC
SCK
S I
VCC
HOLD
SCK
SI
VCC
HOLD
SCK
SI
Bottom View
8-ball dBGA2
8
7
6
5
GND
WP
CS
SO
1
2
3
4
HOLD
VCC
SCK
CS
SO
WP
GND
SI
8-lead SOIC
Bottom View
1
2
3
4
8-lead SAP
8
7
6
5
8
7
6
5
1
2
3
4
CS
SO
WP
GND
VCC
HOLD
SCK
SI
SPI Serial
EEPROMs
128K (16,384 x 8)
256K (32,768 x 8)
AT25128A
AT25256A
3368H–SEEPR–8/05
1

Related parts for AT25128A-W1.8-11

AT25128A-W1.8-11 Summary of contents

Page 1

... TSSOP, 8-ball dBGA2 and 8-lead SAP packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions. The AT25128A/256A is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa- rate Erase cycle is required before Write ...

Page 2

... Input Capacitance (CS, SCK, SI, WP, HOLD) IN Note: 1. This parameter is characterized and is not 100% tested. AT25128A/256A 2 Block Write protection is enabled by programming the status register with top ¼, top ½ or entire array of write protection. Separate Program Enable and Program Disable instructions are provided for additional data protection. Hardware data protection is pro- vided via the WP pin to protect against inadvertent write attempts to the status register ...

Page 3

... 3.6 ≤ V ≤ 5. −1 0. 1.8V ≤ V ≤ 3. −100 µ − = 40° 85° Voltage 4.5−5.5 2.7−5.5 1.8−5.5 4.5−5.5 2.7−5.5 1.8−5.5 4.5−5.5 2.7−5.5 1.8−5.5 4.5−5.5 2.7−5.5 1.8−5.5 AT25128A/256A = +1.8V to +5.5V, CC Min Typ Max 1.8 5.5 2.7 5.5 4.5 5.5 9.0 10.0 5.0 7.0 2.2 3.5 0.2 3.0 0.5 3.0 2.0 5.0 −3.0 3.0 −3.0 3.0 − 0.5 ...

Page 4

... Hold to Output High Output Disable Time DIS t Write Cycle Time WC (1) Endurance 5.0V, 25°C, Page Mode Note: 1. This parameter is characterized and is not 100% tested. Contact Atmel for further information. AT25128A/256A 4 − − = 40° 85° 40°C to +125° Voltage Min 4.5−5.5 20 2.7− ...

Page 5

... WPEN bit in the status register is “0”. This will allow the user to install the AT25128A/256A in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “ ...

Page 6

... Figure 2. SPI Serial Interface AT25128A/256A 6 AT25128A/256A 3368H–SEEPR–8/05 ...

Page 7

... The AT25128A/256A is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT25128A/256A utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in see Table 5. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. ...

Page 8

... WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25128A/256A is divided into four array segments. Top quarter (1/4), top half (1/2), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be read only. The block write protec- tion levels and corresponding status register control bits are shown in Table 8 ...

Page 9

... Write cycle has ended. Only the Read Status Register instruction is enabled during the Write programming cycle. The AT25128A/256A is capable of a 64-byte Page Write operation. After each byte of data is received, the six low order address bits are internally incremented by one; the high order bits of the address will remain constant ...

Page 10

... Timing Diagrams (for SPI Mode 0 (0, 0)) Figure 3. Synchronous Data Timing CSS V IH SCK HI Figure 4. WREN Timing Figure 5. WRDI Timing AT25128A/256A VALID IN t CSH DIS HI-Z 3368H–SEEPR–8/05 ...

Page 11

... Figure 6. RDSR Timing CS 0 SCK SI INSTRUCTION HIGH IMPEDANCE SO Figure 7. WRSR Timing Figure 8. READ Timing 3368H–SEEPR–8/ MSB AT25128A/256A DATA OUT ...

Page 12

... Figure 9. WRITE Timing Figure 10. HOLD Timing CS SCK HOLD SO AT25128A/256A 3368H–SEEPR–8/05 ...

Page 13

... AT25128AY4-10YU-1.8 (3) AT25128A-W2.7-11 (3) AT25128A-W1.8-11 Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables. 2. “U” designates Green package + RoHS compliant. 3. Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please Contact Serial EEPROM Marketing ...

Page 14

... Ball Grid Array Package (dBGA2) 8A2 8-lead, 4.4 mm Body, Thin Shrink Small Outline Package (TSSOP) 8Y4 8-lead, 6. 4.90 mm Body, Dual Footprint, Non-leaded, Small Array Package (SAP) − 2.7 Low-voltage (2.7V to 5.5V) − 1.8 Low-voltage (1.8V to 5.5V) AT25128A/256A 14 (1) Package 8P3 8S1 8S2 8A2 8P3 8S1 8S2 ...

Page 15

... Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 2325 Orchard Parkway San Jose, CA 95131 R 3368H–SEEPR–8/ TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) AT25128A/256A End View COMMON DIMENSIONS (Unit of Measure = inches) MIN MAX SYMBOL NOM A – – 0.210 A2 ...

Page 16

... JEDEC SOIC Top View e Side View Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R AT25128A/256A TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing ...

Page 17

... Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm. 2325 Orchard Parkway San Jose, CA 95131 R 3368H–SEEPR–8/ ∅ End View TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) AT25128A/256A E1 L COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A 1.70 2.16 A1 0.05 0. ...

Page 18

... A1 BALL PAD CORNER e (e1) 1. Dimension 'b' is measured at the maximum solder ball diameter. This drawing is for general information only. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R AT25128A/256A Top View A1 BALL PAD CORNER (d1) Bottom View ...

Page 19

... Dimension D and determined at Datum Plane H. 2325 Orchard Parkway San Jose, CA 95131 R 3368H–SEEPR–8/ TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) AT25128A/256A L1 L End View COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL D 2.90 3.00 3 ...

Page 20

... SAP PIN 1 INDEX AREA D E 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R AT25128A/256A 20 A PIN COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN A – A1 0.00 D 5.80 E 4.70 D1 2.85 E1 2. 0.50 TITLE 8Y4, 8-lead (6.00 x 4.90 mm Body) SOIC Array Package (SAP ...

Page 21

... Atmel Corporation 2005. All rights reserved. Atmel marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 ...

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