M95512-D-RCS3G/AB STMICROELECTRONICS [STMicroelectronics], M95512-D-RCS3G/AB Datasheet

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M95512-D-RCS3G/AB

Manufacturer Part Number
M95512-D-RCS3G/AB
Description
512 Kbit serial SPI bus EEPROM with high-speed clock
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
Features
September 2010
Compatible with the Serial Peripheral Interface
(SPI) bus
Memory array
– 512 Kb (64 Kbytes) of EEPROM
– Page size: 128 bytes
Additional Write lockable Page (Identification
page)
Write
– Byte Write within 5 ms
– Page Write within 5 ms
Write Protect: quarter, half or whole memory
array
High-speed clock frequency (20 MHz)
Single supply voltage: 1.8 V to 5.5 V
More than 1 Million Write cycles
More than 40-year data retention
Enhanced ESD Protection
Packages
– ECOPACK2® (RoHS compliant and
Halogen-free)
Doc ID 11124 Rev 13
512 Kbit serial SPI bus EEPROM
M95512-R M95512-W
with high-speed clock
2 × 3 mm (MLP)
UFDFPN8 (MB)
TSSOP8 (DW)
150 mils width
169 mils width
WLCSP (CS)
SO8 (MN)
M95512-DR
www.st.com
1/48
1

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M95512-D-RCS3G/AB Summary of contents

Page 1

... More than 40-year data retention ■ Enhanced ESD Protection ■ Packages – ECOPACK2® (RoHS compliant and Halogen-free) September 2010 M95512-R M95512-W 512 Kbit serial SPI bus EEPROM with high-speed clock UFDFPN8 (MB) 2 × (MLP) Doc ID 11124 Rev 13 M95512-DR SO8 (MN) ...

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... Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Status Register (RDSR 6.3.1 2/ Operating supply voltage Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Doc ID 11124 Rev 13 M95512-W, M95512-R ...

Page 3

... Read Identification Page (available only in M95512-DR devices 6.8 Write Identification Page (available only in M95512-DR devices 6.9 Read Lock Status (available only in M95512-DR devices 6.10 Lock ID (available only in M95512-DR devices ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . 29 8 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 ...

Page 4

... DC characteristics (current and new M95512-R and M95512-DR products Table 16. AC characteristics (current M95512-W products Table 17. AC characteristics (New M95512-W products Table 18. AC characteristics (current and new M95512-R and M95512-DR products Table 19. SO8N – 8 lead plastic small outline, 150 mils body width, package mechanical data ...

Page 5

... M95512-W, M95512-R List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. SO8, TSSOP8 and UFDFPN8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. WLCSP connections (top view, marking side, with balls on the underside Figure 4. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7 ...

Page 6

... SPI-compatible bus. In the rest of the document these devices are referred to as M95512, unless otherwise specified. The M95512-DR also offers an additional page, named the Identification Page (128 bytes) which can be written and (later) permanently locked in Read-only mode. This Identification Page offers flexibility in the application board production line can be used to store unique identification parameters and/or parameters specific to the production line ...

Page 7

... M95512-W, M95512-R Table 1. Signal names Signal name HOLD Caution: As EEPROM cells loose their charge (and so their binary value) when exposed to ultra violet (UV) light, EEPROM dice delivered in wafer form or in WLCSP package by STMicroelectronics must never be exposed to UV light. ...

Page 8

... Input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven low. 8/48 must be held stable and within the specified valid range: CC Table 13 and Table 15). These signals are described next. Doc ID 11124 Rev 13 M95512-W, M95512 ...

Page 9

... M95512-W, M95512-R 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either high or low, and must be stable during all write instructions. ...

Page 10

... SDO SDI SCK SPI Memory R R Device S W HOLD Figure 4) ensures that no device is selected if the Bus requirement is met. SHCH Doc ID 11124 Rev 13 M95512-W, M95512 SPI Memory SPI Memory R Device Device HOLD ...

Page 11

... M95512-W, M95512-R 3.1 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: ● CPOL=0, CPHA=0 ● CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). ...

Page 12

... CC CC Table 8 and Table 10). (min rises continuously from V CC and Table 10 and the rise time must not vary faster than 1 V/µs. Doc ID 11124 Rev 13 M95512-W, M95512-R CC Table 8 and / reaches a valid and CC (max)] range defined in Table During this ...

Page 13

... M95512-W, M95512-R 4.1.4 Power-down During power-down (continuous decrease in V defined in Table 8 ● deselected (Chip Select (S) should be allowed to follow the voltage applied on V ● in Standby Power mode (that is there should not be any internal write cycle in progress). 4.2 Active Power and Standby Power modes When Chip Select (S) is low, the device is selected, and in the Active Power mode. The device consumes I When Chip Select (S) is high, the device is deselected ...

Page 14

... Table 2. Write-protected block size Status register bits BP1 14/48 Section 6.3: Read Status Register (RDSR) Protected block BP0 0 none 1 Upper quarter 0 Upper half 1 Whole memory Doc ID 11124 Rev 13 M95512-W, M95512-R for a Protected array addresses none C000h - FFFFh 8000h - FFFFh 0000h - FFFFh ...

Page 15

... M95512-W, M95512-R 5 Memory organization The memory is organized as shown in Figure 7. Block diagram HOLD Figure 7. High Voltage Control Logic I/O Shift Register Address Register and Counter Doc ID 11124 Rev 13 Memory organization Generator Data Register Status Register 1 Page X Decoder Size of the Read only ...

Page 16

... Instructions 6 Instructions Each instruction starts with a single-byte code, as summarized invalid instruction is sent (one not contained in deselects itself. Table 3. M95512-W and M95512-R instruction set Instruction WREN WRDI RDSR Read Status Register WRSR READ Read from Memory Array WRITE Table 4. M95512-DR instruction set ...

Page 17

... M95512-W, M95512-R 6.1 Write Enable (WREN) The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state ...

Page 18

... Write Status Register (WRSR) instruction is no longer accepted for execution. Table 5. Status register format b7 SRWD Status Register Write Protect 18/48 Table 5) becomes protected against Write Doc ID 11124 Rev 13 M95512-W, M95512-R Figure 10. BP1 BP0 WEL Block Protect Bits Write Enable Latch Bit Write In Progress Bit b0 WIP ...

Page 19

... M95512-W, M95512-R Figure 10. Read Status Register (RDSR) sequence High Impedance Instruction Status Register Out MSB Doc ID 11124 Rev 13 Instructions Status Register Out MSB 7 AI02031E 19/48 ...

Page 20

... Figure 11. Write Status Register (WRSR) sequence 20/48 (specified in Table complete. W Table Instruction 7 High Impedance MSB Doc ID 11124 Rev 13 M95512-W, M95512-R and Table 18). The instruction sequence Status Register AI02282D ...

Page 21

... M95512-W, M95512-R Table 6. Protection modes W SRWD Signal Bit 1 0 Software 0 0 Protected 1 1 Hardware 0 1 Protected 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in The protection features of the device are summarized in When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial ...

Page 22

... Chip Select (S) is first driven 16-Bit Address MSB Doc ID 11124 Rev 13 M95512-W, M95512 Data Out 1 Data Out MSB AI01793D ...

Page 23

... M95512-W, M95512-R 6.6 Write to Memory Array (WRITE) As shown in Figure low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input data. The self-timed Write cycle triggered by the rising edge of Chip Select (S) continues for ...

Page 24

... Address Data Byte 2 Data Byte Doc ID 11124 Rev 13 M95512-W, M95512 Data Byte Data Byte ...

Page 25

... M95512-W, M95512-R 6.7 Read Identification Page (available only in M95512-DR devices) The Identification Page (128 bytes additional page which can be written and (later) permanently locked in Read-only mode. Reading this page is achieved with the Read Identification Page instruction (see The Chip Select signal (S) is first driven low, the bits of the instruction byte and address bytes are then shifted in, on Serial Data input (D) ...

Page 26

... Instructions 6.8 Write Identification Page (available only in M95512-DR devices) The Identification Page (128 bytes additional page which can be written and (later) permanently locked in Read-only mode. Writing this page is achieved with the Write Identification Page instruction (see bits of the instruction byte, address byte, and at least one data byte are then shifted in on Serial Data input (D) ...

Page 27

... M95512-W, M95512-R 6.9 Read Lock Status (available only in M95512-DR devices) The Read Lock Status instruction (see locked (or not) in read-only mode. The Read Lock Status sequence is defined with the Chip Select (S) first driven low. The bits of the instruction byte and address bytes are then shifted in on Serial Data input (D) ...

Page 28

... Chip Select (S) being driven high byte boundary (after the eighth bit, b0, of the last data byte that was latched in) ● if the Identification page is locked by the Lock Status bit Figure 18. Lock ID sequence 28/48 Doc ID 11124 Rev 13 M95512-W, M95512-R ...

Page 29

... It is therefore recommended to write by words of 4 bytes in order to benefit from the larger amount of Write cycles. The M95512-W, M95512-R and M95512-DR devices are qualified at 1 million (1 000 000) Write cycles, using a cycling routine that writes to the device by multiples of 4-byte packets. ...

Page 30

... Compliant with JEDEC Std J-STD-020D (for small body, Sn- assembly), the ST ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100pF, R1=1500 , R2=500 ) 30/48 Table 7 Parameter (2) Doc ID 11124 Rev 13 M95512-W, M95512-R may cause permanent damage to Min. Max. –40 130 °C –65 150 ° ...

Page 31

... Table 8. Operating conditions (M95512-W device grade 6) Symbol V Supply voltage CC T Ambient operating temperature (device grade 6) A Table 9. Operating conditions (M95512-W device grade 3) Symbol V Supply voltage CC T Ambient operating temperature (device grade 6) A Table 10. Operating conditions (M95512-R and M95512-DR) Symbol ...

Page 32

... 2.5 V < 2.5 V and and 2.5 V and and I CC Doc ID 11124 Rev 13 M95512-W, M95512-R Min. Max 2 Min. Max ± ± MHz < ...

Page 33

... IH V Output low voltage OL V Output high voltage OH 1. New products are identified by process letter K. 2. Characterized value, not tested in production. Table 15. DC characteristics (current and new M95512-R and M95512-DR products) Symbol Parameter I Input leakage current LI I Output leakage current LO I Supply current (Read) ...

Page 34

... Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output High-Z Write time Doc ID 11124 Rev 13 M95512-W, M95512-R = –40 to 125 °C (device grade 3) A Min. Max. Unit D.C. 5 MHz ...

Page 35

... Write time New products are identified by process letter must never be less than the shortest possible clock period Value guaranteed by characterization, not 100% tested in production. (1) M95512-W products) = 2 – ° Min. Parameter 2 5 ...

Page 36

... DC and AC parameters Table 18. AC characteristics (current and new M95512-R and M95512-DR products) Test conditions: V Symbol Alt Clock frequency C SCK active setup time SLCH CSS1 not active setup time SHCH CSS2 deselect time SHSL active hold time ...

Page 37

... M95512-W, M95512-R Figure 20. Serial input timing S tCHSL C tDVCH D Q Figure 21. Hold timing HOLD tSLCH tCH tCHCL tCL tCHDX MSB IN High impedance tHLCH tCLHL tHLQZ Doc ID 11124 Rev 13 DC and AC parameters tSHSL tCHSH tSHCH tCLCH LSB IN tHHCH tCLHH tHHQV AI01448c AI01447d ...

Page 38

... DC and AC parameters Figure 22. Serial output timing S C tCLQV tCLCH tCLQX Q ADDR D LSB IN 38/48 tCH tCHCL tCL tQLQH tQHQL Doc ID 11124 Rev 13 M95512-W, M95512-R tSHSL tSHQZ AI01449f ...

Page 39

... M95512-W, M95512-R 11 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. Figure 23. SO8N – 8 lead plastic small outline, 150 mils body width, package outline A2 1 ...

Page 40

... Doc ID 11124 Rev 13 M95512-W, M95512 TSSOP8AM (1) inches Typ Min Max 0.0472 0.0020 0.0059 0.0394 0.0315 0.0413 0.0075 0.0118 0.0035 0.0079 ...

Page 41

... M95512-W, M95512-R Figure 25. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead 2 × 3 mm, package outline 1. Drawing is not to scale. 2. The central pad (the area the above illustration) is internally pulled to VSS. It must not be connected to any other voltage or signal line on the PCB, for example during the soldering process. ...

Page 42

... Min Max 0.580 0.490 0.670 0.230 0.350 0.322 1.433 1.548 1.901 2.016 1.000 0.866 0.500 0.433 0.284 0.453 8 0.110 0.060 Doc ID 11124 Rev 13 M95512-W, M95512 Orientation reference e2 A Detail Bump side ME_1Cc (1) inches Typ Min ...

Page 43

... M95512-W, M95512-R 12 Part numbering Table 23. Ordering information scheme Example: Device type M95 = SPI serial access EEPROM Device function 512 = 512 Kbit (65536 × 8) 512-D = 512 Kbit (65536 × 8) plus Identification page Operating voltage Package MN = SO8 (150 mil width) ...

Page 44

... To identify current from new devices, please contact your nearest ST sales office. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. Table 24. Available M95512 products (package, voltage range, temperature grade) Package SO8 (MN) TSSOP (DW) ...

Page 45

... AEC-Q100-002 compliance. Device Grade 5.0 information clarified. t HHQX t , respectively. CLHH M95512 part number with 4.5V to 5.5V operating voltage range removed (related tables removed). Document status changed to Preliminary Data. Updated Figure 4: Bus master and memory devices on the SPI bus Figure 21: Hold timing. Power On Reset ...

Page 46

... Plating technology scheme. The device endurance is specified at more than 1 000 000 (1 million) 8 cycles (corrected on cover page). M95512-W is now available in the device grade 3 (automotive temperature range), see Table 8 on page Section 4.1: Supply voltage (VCC) on page 12 Section 6.4: Write Status Register (WRSR) on page 20 Write to Memory Array (WRITE) on page 23 ...

Page 47

... Section 6.7: Read Identification Page (available only in M95512-DR devices) 11 – Section 6.8: Write Identification Page (available only in M95512-DR devices) – Section 6.9: Read Lock Status (available only in M95512-DR devices) – Section 6.10: Lock ID (available only in M95512-DR devices) Data related to new products are no longer preliminary. 12 Note 2 updated in ...

Page 48

... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 48/48 Please Read Carefully: © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 11124 Rev 13 M95512-W, M95512-R ...

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