IC EEPROM 512KBIT 2MHZ 8TSSOP

M95512-RDW6P

Manufacturer Part NumberM95512-RDW6P
DescriptionIC EEPROM 512KBIT 2MHZ 8TSSOP
ManufacturerSTMicroelectronics
M95512-RDW6P datasheet
 

Specifications of M95512-RDW6P

Format - MemoryEEPROMs - SerialMemory TypeEEPROM
Memory Size512K (64K x 8)Speed2MHz
InterfaceSPI, 3-Wire SerialVoltage - Supply1.8 V ~ 5.5 V
Operating Temperature-40°C ~ 85°CPackage / Case8-TSSOP
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Features
Compatible with the Serial Peripheral Interface
(SPI) bus
Memory array
– 512 Kb (64 Kbytes) of EEPROM
– Page size: 128 bytes
Additional Write lockable Page (Identification
page)
Write
– Byte Write within 5 ms
– Page Write within 5 ms
Write Protect: quarter, half or whole memory
array
High-speed clock frequency (20 MHz)
Single supply voltage: 1.8 V to 5.5 V
More than 1 Million Write cycles
More than 40-year data retention
Enhanced ESD Protection
Packages
– ECOPACK2® (RoHS compliant and
Halogen-free)
April 2011
M95512-R M95512-W
512 Kbit serial SPI bus EEPROM
with high-speed clock
UFDFPN8 (MB)
2 × 3 mm (MLP)
Doc ID 11124 Rev 14
M95512-DR
SO8 (MN)
150 mils width
TSSOP8 (DW)
169 mils width
WLCSP (CS)
1/48
www.st.com
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M95512-RDW6P Summary of contents

  • Page 1

    ... More than 40-year data retention ■ Enhanced ESD Protection ■ Packages – ECOPACK2® (RoHS compliant and Halogen-free) April 2011 M95512-R M95512-W 512 Kbit serial SPI bus EEPROM with high-speed clock UFDFPN8 (MB) 2 × (MLP) Doc ID 11124 Rev 14 M95512-DR SO8 (MN) ...

  • Page 2

    ... Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Status Register (RDSR 6.3.1 2/ Operating supply voltage Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Doc ID 11124 Rev 14 M95512-DR, M95512-W, M95512-R ...

  • Page 3

    ... Read Identification Page (available only in M95512-DR devices 6.8 Write Identification Page (available only in M95512-DR devices 6.9 Read Lock Status (available only in M95512-DR devices 6.10 Lock ID (available only in M95512-DR devices ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . 30 8 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1 Power-up state ...

  • Page 4

    ... Table 12. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 13. Memory cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 14. DC characteristics (current M95512-W products Table 15. DC characteristics (new M95512-W products Table 16. DC characteristics (current and new M95512-R and M95512-DR products Table 17. AC characteristics (current M95512-W products Table 18. AC characteristics (New M95512-W products Table 19. ...

  • Page 5

    ... M95512-DR, M95512-W, M95512-R List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. SO8, TSSOP8 and UFDFPN8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. WLCSP connections (top view, marking side, with balls on the underside Figure 4. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7 ...

  • Page 6

    ... SPI-compatible bus. In the rest of the document these devices are referred to as M95512, unless otherwise specified. The M95512-DR also offers an additional page, named the Identification Page (128 bytes) which can be written and (later) permanently locked in Read-only mode. This Identification Page offers flexibility in the application board production line can be used to store unique identification parameters and/or parameters specific to the production line ...

  • Page 7

    ... M95512-DR, M95512-W, M95512-R Table 1. Signal names Signal name HOLD Figure 2. SO8, TSSOP8 and UFDFPN8 connections 1. See Section 11: Package mechanical data Figure 3. WLCSP connections (top view, marking side, with balls on the underside) Caution: As EEPROM cells loose their charge (and so their binary value) when exposed to ultra violet (UV) light, EEPROM dice delivered in wafer form or in WLCSP package by STMicroelectronics must never be exposed to UV light ...

  • Page 8

    ... Input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven low. 8/48 must be held stable and within the specified valid range: CC Table 14 and Table 16). These signals are described next. Doc ID 11124 Rev 14 M95512-DR, M95512-W, M95512 ...

  • Page 9

    ... M95512-DR, M95512-W, M95512-R 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either high or low, and must be stable during all write instructions. ...

  • Page 10

    ... C line is pulled low (while the S line is pulled high). This ensures that S and C do not become high at the same time, and so, that the t The typical value 100 k ,. 10/48 requirement is met. SHCH Doc ID 11124 Rev 14 M95512-DR, M95512-W, M95512-R Figure 4) ensures that each ...

  • Page 11

    ... M95512-DR, M95512-W, M95512-R 3.1 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: ● CPOL=0, CPHA=0 ● CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C) ...

  • Page 12

    ... CC CC Table 8 and Table 10). (min rises continuously from V CC and Table 10 and the rise time must not vary faster than 1 V/µs. Doc ID 11124 Rev 14 M95512-DR, M95512-W, M95512-R CC Table 8 and / reaches a valid and CC (max)] range defined in Table During this ...

  • Page 13

    ... M95512-DR, M95512-W, M95512-R 4.1.4 Power-down During power-down (continuous decrease in V defined in Table 8 ● deselected (Chip Select (S) should be allowed to follow the voltage applied on V ● in Standby Power mode (that is there should not be any internal write cycle in progress). 4.2 Active Power and Standby Power modes When Chip Select (S) is low, the device is selected, and in the Active Power mode ...

  • Page 14

    ... Status register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. See detailed description of the Status register bits. Table 2. Write-protected block size Status register bits BP1 14/48 M95512-DR, M95512-W, M95512-R Hold Condition Section 6.3: Read Status Register (RDSR) Protected block BP0 0 none 1 Upper quarter 0 Upper half ...

  • Page 15

    ... M95512-DR, M95512-W, M95512-R 4.5 Data protection and protocol control Non-volatile memory devices can be used in environments that are particularly noisy, and within applications that could experience problems if memory bytes are corrupted. Consequently, the device features the following data protection mechanisms: ● Write and Write Status register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. ● ...

  • Page 16

    ... Memory organization 5 Memory organization The memory is organized as shown in Figure 7. Block diagram 16/48 M95512-DR, M95512-W, M95512-R Figure 7. Doc ID 11124 Rev 14 ...

  • Page 17

    ... M95512-DR, M95512-W, M95512-R 6 Instructions Each instruction starts with a single-byte code, as summarized invalid instruction is sent (one not contained in deselects itself. Table 3. M95512-W and M95512-R instruction set Instruction WREN WRDI RDSR Read Status Register WRSR READ Read from Memory Array WRITE Table 4. M95512-DR instruction set ...

  • Page 18

    ... WRITE instruction completion. Figure 9. Write Disable (WRDI) sequence 18/ send this instruction to the device, Chip Select (S) is driven low Instruction High Impedance 9, to send this instruction to the device, Chip Select (S) is driven low Instruction D High Impedance Q Doc ID 11124 Rev 14 M95512-DR, M95512-W, M95512 AI02281E AI03750D ...

  • Page 19

    ... M95512-DR, M95512-W, M95512-R 6.3 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device ...

  • Page 20

    ... Instructions Figure 10. Read Status Register (RDSR) sequence High Impedance Q 20/ Instruction Status Register Out MSB Doc ID 11124 Rev 14 M95512-DR, M95512-W, M95512-R Status Register Out MSB 7 AI02031E ...

  • Page 21

    ... M95512-DR, M95512-W, M95512-R 6.4 Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before a WRSR instruction can be accepted, a Write Enable (WREN) instruction must have been executed. The Write Status Register (WRSR) instruction is issued by driving Chip Select (S) low, sending the instruction code and the data byte on Serial Data input (D) and driving Chip Select (S) high ...

  • Page 22

    ... The values in the BP1 and BP0 bits can be changed Status Register is Hardware write protected The values in the BP1 and (HPM) BP0 bits cannot be changed Doc ID 11124 Rev 14 M95512-DR, M95512-W, M95512-R Memory content (1) Protected area Unprotected area Ready to accept Write Protected Write instructions Ready to accept ...

  • Page 23

    ... M95512-DR, M95512-W, M95512-R 6.5 Read from Memory Array (READ) As shown in Figure low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data Output (Q). ...

  • Page 24

    ... Write in Progress 13, Chip Select (S) is driven high after the eighth bit of the data byte is internally executed as a sequence of two consecutive Instruction 16-Bit Address High Impedance Doc ID 11124 Rev 14 M95512-DR, M95512-W, M95512-R Figure 14., the next byte Data Byte ...

  • Page 25

    ... M95512-DR, M95512-W, M95512-R Figure 14. Page Write (WRITE) sequence Instruction 16-Bit Address Data Byte 2 Data Byte Doc ID 11124 Rev Data Byte Data Byte Instructions AI01796D 25/48 ...

  • Page 26

    ... Instructions 6.7 Read Identification Page (available only in M95512-DR devices) The Identification Page (128 bytes additional page which can be written and (later) permanently locked in Read-only mode. Reading this page is achieved with the Read Identification Page instruction (see The Chip Select signal (S) is first driven low, the bits of the instruction byte and address bytes are then shifted in, on Serial Data input (D) ...

  • Page 27

    ... M95512-DR, M95512-W, M95512-R 6.8 Write Identification Page (available only in M95512-DR devices) The Identification Page (128 bytes additional page which can be written and (later) permanently locked in Read-only mode. Writing this page is achieved with the Write Identification Page instruction (see bits of the instruction byte, address byte, and at least one data byte are then shifted in on Serial Data input (D) ...

  • Page 28

    ... Instructions 6.9 Read Lock Status (available only in M95512-DR devices) The Read Lock Status instruction (see locked (or not) in read-only mode. The Read Lock Status sequence is defined with the Chip Select (S) first driven low. The bits of the instruction byte and address bytes are then shifted in on Serial Data input (D) ...

  • Page 29

    ... M95512-DR, M95512-W, M95512-R The instruction is not accepted, and so not executed, under the following conditions: ● if the Write Enable Latch (WEL) bit has not been set to 1 (by previously executing a Write Enable instruction) ● if Status register bits (BP1,BP0) = (1,1) ● write cycle is already in progress ● ...

  • Page 30

    ... It is therefore recommended to write data by word (4 bytes) at address 4*N (where integer) in order to benefit from the larger amount of Write cycles. The M95512-W, M95512-R and M95512-DR devices are qualified at 1 million (1 000 000) Write cycles, using a cycling routine that writes to the device by multiples of 4-byte packets. ...

  • Page 31

    ... M95512-DR, M95512-W, M95512-R 9 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...

  • Page 32

    ... Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 8. Operating conditions (M95512-W device grade 6) Symbol V Supply voltage ...

  • Page 33

    ... M95512-DR, M95512-W, M95512-R Table 12. Capacitance Symbol C Output capacitance (Q) OUT Input capacitance ( Input capacitance (other pins) 1. Not 100% tested. Table 13. Memory cell characteristics Symbol Parameter N Endurance cycle Note: This parameter is not tested but established by characterization and qualification. For endurance estimates in a specific application, please refer to AN2014. ...

  • Page 34

    ... V Output low voltage OL V Output high voltage the application uses the M95512-R or M95512-DR with 2.5 V < VCC < 5.5 V and -40 °C < TA < +85 °C, please refer to Table 13 and Table 14 instead of the above table. 2. Current products are identified by process letters AB. 3. New products are identified by process letter K. ...

  • Page 35

    ... M95512-DR, M95512-W, M95512-R Table 17. AC characteristics (current V = 2 Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX DH t HHCH t HLCH t CLHL t CLHH ( SHQZ DIS t t CLQV CLQX ...

  • Page 36

    ... New products are identified by process letter must never be less than the shortest possible clock period Value guaranteed by characterization, not 100% tested in production. 36/48 (1) M95512-W products) = 2 – ° Min. Parameter 2 5 (max) C Doc ID 11124 Rev 14 M95512-DR, M95512-W, M95512-R Max. Min. Max ...

  • Page 37

    ... M95512-DR, M95512-W, M95512-R Table 19. AC characteristics (current and new M95512-R and M95512-DR products) Test conditions: V Symbol Alt Clock frequency C SCK active setup time SLCH CSS1 not active setup time SHCH CSS2 deselect time SHSL active hold time CHSH CSH t S not active hold time ...

  • Page 38

    ... DC and AC parameters Figure 20. Serial input timing S tCHSL C tDVCH D Q Figure 21. Hold timing HOLD 38/48 tSLCH tCH tCHCL tCL tCHDX MSB IN High impedance tHLCH tCLHL tHLQZ Doc ID 11124 Rev 14 M95512-DR, M95512-W, M95512-R tSHSL tCHSH tSHCH tCLCH LSB IN tHHCH tCLHH tHHQV AI01448c AI01447d ...

  • Page 39

    ... M95512-DR, M95512-W, M95512-R Figure 22. Serial output timing S C tCLQV tCLCH tCLQX Q ADDR D LSB IN tCH tCHCL tCL tQLQH tQHQL Doc ID 11124 Rev 14 DC and AC parameters tSHSL tSHQZ AI01449f 39/48 ...

  • Page 40

    ... Doc ID 11124 Rev 14 M95512-DR, M95512-W, M95512 45˚ c 0.25 mm GAUGE PLANE SO-A (1) inches Typ Min 0.0039 0.0492 0.011 0.0067 0.1929 0.189 0.2362 ...

  • Page 41

    ... M95512-DR, M95512-W, M95512-R Figure 24. TSSOP8 – 8 lead thin shrink small outline, package outline Drawing is not to scale. 2. The central pad (area the above illustration) is internally pulled to VSS. It must not be connected to any other voltage or signal line on the PCB, for example during the soldering process. ...

  • Page 42

    ... Doc ID 11124 Rev 14 M95512-DR, M95512-W, M95512 UFDFPN-01 (1) inches Typ Min Max 0.0217 0.0197 0.0236 0.0008 0 0.0020 0.0098 0.0079 0.0118 0.0787 ...

  • Page 43

    ... M95512-DR, M95512-W, M95512-R Figure 26. WLCSP-R – 8-bump wafer-length chip-scale package outline Orientation reference Bump eee Z 1. Drawing is not to scale. Table 23. WLCSP-R – 8-bump wafer-length chip-scale package mechanical data Symbol ( (number of terminals) aaa eee 1. Values in inches are converted from mm and rounded to 4 decimal digits. ...

  • Page 44

    ... The process letters only appear in the product ordering codes of device grade 3 devices. For other devices only given here as an indication of how to differentiate current from new products. To identify current from new devices, please contact your nearest ST sales office. 44/48 M95512 (1) . ® (RoHS compliant) Doc ID 11124 Rev 14 M95512-DR, M95512-W, M95512-R – /AB ...

  • Page 45

    ... AEC-Q100-002 compliance. Device Grade 5.0 information clarified. t HHQX t , respectively. CLHH M95512 part number with 4.5V to 5.5V operating voltage range removed (related tables removed). Document status changed to Preliminary Data. Updated Figure 4: Bus master and memory devices on the SPI bus Figure 21: Hold timing. Power On Reset ...

  • Page 46

    ... Plating technology scheme. The device endurance is specified at more than 1 000 000 (1 million) 8 cycles (corrected on cover page). M95512-W is now available in the device grade 3 (automotive temperature range), see Table 8 on page Section 4.1: Supply voltage (VCC) on page 12 Section 6.4: Write Status Register (WRSR) on page 21 ...

  • Page 47

    ... Section 6.7: Read Identification Page (available only in M95512-DR devices) 11 – Section 6.8: Write Identification Page (available only in M95512-DR devices) – Section 6.9: Read Lock Status (available only in M95512-DR devices) – Section 6.10: Lock ID (available only in M95512-DR devices) Data related to new products are no longer preliminary. 12 Note 3 updated in ...

  • Page 48

    ... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 48/48 Please Read Carefully: © 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 11124 Rev 14 M95512-DR, M95512-W, M95512-R ...