W9812G6GH-6 WINBOND [Winbond], W9812G6GH-6 Datasheet
W9812G6GH-6
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W9812G6GH-6 Summary of contents
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... Precharge Command........................................................................................................ 10 7.16 Self Refresh Command..................................................................................................... 10 7.17 Power Down Mode............................................................................................................ 11 7.18 No Operation Command ................................................................................................... 11 7.19 Deselect Command .......................................................................................................... 11 7.20 Clock Suspend Mode........................................................................................................ 11 8. OPERATION MODE...................................................................................................................... 12 9. ELECTRICAL CHARACTERISTICS ............................................................................................. 13 9.1 Absolute Maximum Ratings .............................................................................................. 13 9.2 Recommended DC Operating Conditions ........................................................................ 13 9.3 Capacitance ...................................................................................................................... BANKS X 16 BITS SDRAM Publication Release Date:Aug. 13, 2007 - 1 - W9812G6GH Revision A06 ...
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... Timing Chart of Burst Stop Cycle (Burst Stop Command) ............................................... 38 11.20 Timing Chart of Burst Stop Cycle (Precharge Command)................................................ 38 11.21 CKE/DQM Input Timing (Write Cycle) .............................................................................. 39 11.22 CKE/DQM Input Timing (Read Cycle) .............................................................................. 40 12. PACKAGE SPECIFICATION......................................................................................................... 41 12.1 54L TSOP (II)-400 mil ....................................................................................................... 41 13. REVISION HISTORY..................................................................................................................... 42 W9812G6GH Publication Release Date:Aug. 13, 2007 - 2 - Revision A06 ...
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... Interface: LVTTL • Packaged in TSOP II 54 pin, 400 mil - 0.80 • W9812G6GH is using Lead free materials • RoHS compliant 3. AVAILABLE PART NUMBER PART NUMBER W9812G6GH-6 166MHz/CL3 W9812G6GH-6C 166MHz/CL3 W9812G6GH-6I 166MHz/CL3 W9812G6GH-75 133MHz/CL3 MAXIMUM SELF SPEED REFRESH CURRENT W9812G6GH ...
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... CS BS0 BS1 A10/ W9812G6GH DQ15 DQ14 51 50 DQ13 DQ12 48 DQ11 DQ10 45 DQ9 DQ8 ...
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... Ground Ground for input buffers and logic circuit inside DRAM. Separated power from V for I/O Buffer improve noise. Separated ground from V Buffer improve noise W9812G6GH DESCRIPTION , used for output buffers used for output buffers to SS Publication Release Date:Aug. 13, 2007 -Revision A06 ...
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... SENSE A MPLIFIER DATA CONTRO L CIRCUIT CO LUM N DE COD CELL ARRAY D E BANK # SEN SE AM PLIFIER Publication Release Date:Aug. 13, 2007 - 6 - W9812G6GH C OLUM N D ECO DER CELL ARRAY E C BANK # SENSE A MPLIFIER DM n DQ0 DQ BUFFER ...
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... Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle. pins must be ramp up simultaneously to the specified voltage CCQ ). The maximum time that each bank can be held active is RRD - 7 W9812G6GH CC delay. WE pin RCD Publication Release Date:Aug. 13, 2007 -Revision A06 +0.3V RSC ) ...
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... Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored. W9812G6GH Publication Release Date:Aug. 13, 2007 - 8 - ...
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... (disturb address is A0) No address carry from (disturb addresses are A0 and A1) No address carry from (disturb addresses are A0, A1 and A2) No address carry from ACCESS ADDRESS Publication Release Date:Aug. 13, 2007 - 9 W9812G6GH BURST LENGTH -Revision A06 ...
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... The period between the Auto Refresh command and the next command is specified has been satisfied. Issue of Auto-precharge command is RP and When using the Auto-precharge Command, the interval W9812G6GH . The bank WR are satisfied. This is referred Publication Release Date:Aug. 13, 2007 Revision A06 ...
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... The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. . The input buffers need (min (min). CKS CK Publication Release Date:Aug. 13, 2007 - 11 W9812G6GH ) of the REF -Revision A06 ...
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... Publication Release Date:Aug. 13, 2007 - 12 - W9812G6GH A0−A9 CS RAS CAS WE A11 ...
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... STG T SOLDER OUT SYMBOL MIN. TYP. V 3.0 3 3.0 3.3 CCQ SYMBOL CLK C IO Publication Release Date:Aug. 13, 2007 - 13 W9812G6GH RATING UNIT + 0 -0 °C - °C -55 ~ 150 °C 260 ° MAX. UNIT 3 0.8 V MIN. MAX. UNIT - 3 ...
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... CKE = CC3 CKE = V (Power IL I CC3P down mode) I 120 CC4 I 200 CC5 I CC6 SYMBOL MIN I( O( W9812G6GH -75 UNIT MAX 100 190 2 2 MAX. UNIT 5 µA 5 µ 0.4 V Publication Release Date:Aug. 13, 2007 ...
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... 1.5 CKS t 1.0 CKH t 1.5 CMS t 1.0 CMH t 64 REF t 12 RSC t 72 XSR - 15 W9812G6GH 6C -75 UNIT MAX. MIN. MAX 100000 45 100000 tCK tCK 1000 6 7.5 2 2 ...
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... T 10. If clock rising time ( longer than 1nS 1 ohms AC TEST LOAD and 1nS. T /2-0.5)nS should be added to the parameter W9812G6GH CONDITIONS 1.4V See diagram below 2.4V/0.4V 1/1 nS 1.4V 50 ohms 30pF Publication Release Date:Aug. 13, 2007 Revision A06 ...
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... A0-A11 BS0 CKS CKH CKE CMS CMH t t CMS CMH t t CMS CMH t t CMS CMH CKS CKH - 17 W9812G6GH CMH CMS t t CKS CKH Publication Release Date:Aug. 13, 2007 -Revision A06 ...
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... Read Timing CLK CS RAS CAS WE A0-A11 BS0 Read Command Read CAS Latency Valid Data-Out Publication Release Date:Aug. 13, 2007 - 18 - W9812G6GH Valid Data-Out Burst Length Revision A06 ...
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... CMS Valid Valid Data-Out Data-Out CKS CKH CKS Valid Valid Data-Out Data-Out - 19 W9812G6GH Valid Valid Data-in Data- Valid Valid Data-in Data- ...
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... A5 CAS Latency "0" (Test Mode) A8 "0" Reserved A0 A9 Write Mode A0 A10 "0" A11 A0 "0" BS0 "0" A0 Reserved "0" BS1 W9812G6GH t RSC command A0 Burst Length Sequential A0 Interleave ...
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... RP t RAS t t RCD RCD RBb RAc RBb CBx RAc t AC aw0 aw2 aw3 bx0 bx1 aw1 t RRD Precharge Active Precharge Active Read - 21 W9812G6GH RAS RAS t RCD RBd CAy RBd CBz t AC ...
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... RAS t RCD t RCD RAc CBx RAc aw0 aw1 aw2 aw3 bx0 bx1 t RRD Active AP* Read - 22 - W9812G6GH RAS RAS t RCD RAe RBd CBz CAy RAe RBd ...
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... RAS RAS t RCD RBb RBb CBy ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 t RRD Precharge Active Read - 23 W9812G6GH RAS RCD RAc RAc CAz t AC by1 by4 by5 by6 ...
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... RAS RP t RCD RBb RBb CBy CAC ax3 ax4 ax0 ax2 ax5 ax6 ax7 ax1 t RRD AP* Active Read * AP is the internal precharge start timing - 24 - W9812G6GH RAS t t RAS RP t RCD RAc CAz RAc t CAC t CAC ...
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... RC t RAS t RCD RBb RBb CBy ax4 ax5 ax6 ax7 by0 by1 by2 t RRD Precharge Active Write - 25 W9812G6GH RAS t RAS t RCD RAc RAc CAz by3 by4 by5 by6 by7 CZ0 Active Write Precharge Publication Release Date:Aug ...
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... RC t RAS t RCD RBb CBy RBb ax4 by2 ax5 ax6 ax7 by0 by1 t RRD AP* Active Write * AP is the internal precharge start timing - 26 - W9812G6GH RAS t RCD RAb CAz RAc by5 by3 by4 by6 by7 CZ0 Write Active Publication Release Date:Aug ...
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... RAS t RCD CBx CAy CAm bx0 Ay0 Ay1 a2 bx1 Read Read Read * AP is the internal precharge start timing - 27 W9812G6GH CBz am1 am2 bz0 bz1 bz2 bz3 Ay2 am0 Precharge ...
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... Bank #2 Idle Bank # RAS CAy ax0 ax1 ax3 ax5 ay0 ax2 ax4 Write - 28 - W9812G6GH ay1 ay2 ay4 ay3 Precharge Publication Release Date:Aug. 13, 2007 Revision A06 23 ...
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... RCD RAb RAb AC aw0 aw1 aw2 aw3 AP* Active * AP is the internal precharge start timing - 29 W9812G6GH RAS CAx t AC bx0 bx1 bx2 bx3 Read AP* Publication Release Date:Aug. 13, 2007 -Revision A06 ...
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... Bank # RCD RAb RAb CAx bx0 aw3 Active Write AP the internal precharge start timing - 30 - W9812G6GH RAS RP RAc RAc bx1 bx3 bx2 AP* Active Publication Release Date:Aug. 13, 2007 Revision A06 ...
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... CLK RAS CAS WE BS0,1 A10 A0-A9, A11 DQM CKE DQ All Banks Auto Prechage Refresh (CLK = 100 MHz W9812G6GH Auto Refresh (Arbitrary Cycle) Publication Release Date:Aug. 13, 2007 -Revision A06 ...
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... CKE t CKS DQ All Banks Self Refresh Precharge Entry (CLK = 100 MHz CKS SB Self Refresh Cycle Self Refresh Exit - 32 - W9812G6GH CKS t XSR No Operation / Command Inhibit Arbitrary Cycle Publication Release Date:Aug. 13, 2007 Revision A06 23 ...
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... Bank # CBw CBx t AC av0 av1 av3 aw0 ax0 av2 Single Write - 33 W9812G6GH CBz CBy t AC ay0 az0 az1 az2 az3 Read Publication Release Date:Aug. 13, 2007 -Revision A06 23 ...
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... Violating refresh requirements during power-down may result in a loss of data CAa t CKS ax0 ax1 ax2 ax3 Read Precharge - 34 - W9812G6GH RAa RAa CAx CKS NOP Active Precharge Standby Power Down mode Publication Release Date:Aug. 13, 2007 ...
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... Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. (min). RAS - 35 W9812G6GH Act Act AP Act Publication Release Date:Aug. 13, 2007 ...
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... AP Act tRP tWR AP tRP tWR represents the Write with Auto precharge command. represents the start of internal precharing. represents the Bank Active command W9812G6GH Act AP Act tRP tWR D7 Act Act AP Act tWR tRP D7 Publication Release Date:Aug. 13, 2007 ...
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... Note: The Output data must be masked by DQM to avoid I/O conflict Read Read Read Read W9812G6GH Publication Release Date:Aug. 13, 2007 -Revision A06 ...
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... BST Note: BST represents the Burst stop command PRCG PRCG tWR tWR W9812G6GH PRCG PRCG Publication Release Date:Aug. 13, 2007 Revision A06 11 ...
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... CLK cycle No. External CLK Internal CKE DQM DQM MASK ( DQM MASK ( CKE MASK ( W9812G6GH CKE MASK CKE MASK Publication Release Date:Aug. 13, 2007 -Revision A06 ...
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... External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM W9812G6GH Open Open Open Publication Release Date:Aug. 13, 2007 Revision A06 ...
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... MIN. NOM. NOM. 1.20 0.10 0.15 0.004 0.05 0.002 1.00 0.039 0.40 0.24 0.32 0.009 0.012 0.15 0.006 22.12 22.62 0.871 0.875 22.22 0.400 10.06 10.16 10.26 0.396 11.76 11.96 0.455 11.56 0.463 0.80 0.0315 0.60 0.40 0.50 0.016 0.020 0.80 0.032 0.10 0.71 0.028 - 41 W9812G6GH MAX. 0.047 0.006 0.016 0.905 0.404 0.471 0.024 0.004 Publication Release Date:Aug. 13, 2007 -Revision A06 ...
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... XSR 3,13,14,15 Add -6I grade for Ta= -40 to 85°C Revise transient time t 16 formula for compensation consideration in Notes Characteristics and Operating Condition Important Notice - 42 - W9812G6GH DESCRIPTION min=0.8nS IH AC test condition and calculate T Publication Release Date:Aug. 13, 2007 Revision A06 RC ...