W9812G6GH-6 WINBOND [Winbond], W9812G6GH-6 Datasheet - Page 5

• Manufacturer Part Number: W9812G6GH-6
• Description: 2M X 4 BANKS X 16 BITS SDRAM
• Manufacturer: WINBOND [Winbond]

5. PIN DESCRIPTION
10, 11, 13, 42,
44, 45, 47, 48,
PIN NUMBER
6, 12, 46, 52
23 − 26, 22,
2, 4, 5, 7, 8,
3, 9, 43, 49
50, 51, 53
28, 41, 54
1, 14, 27
29 − 35
20, 21
39, 15
36, 40
19
18
17
16
38
37
PIN NAME
BS0, BS1
A0 − A11
UDQM/
LDQM
V
DQ0 −
DQ15
V
RAS
CAS
CKE
CLK
V
V
WE
NC
CS
CC
SS
CC
SS
Q
Q
Column Address
No Connection No connection
Power (+3.3V)
Power (+3.3V)
Ground for I/O
Row Address
Clock Enable
Write Enable
for I/O Buffer
Input/Output
Clock Inputs
Bank Select
Chip Select
FUNCTION
Data Input/
Address
Ground
Output
Strobe
Strobe
Buffer
Mask
- 5
Multiplexed pins for row and column address.
Row address: A0 − A11. Column address: A0 − A8.
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
the clock, RAS , CAS and WE define the
operation to be executed.
Referred to RAS
Referred to RAS
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
System clock used to sample inputs on the rising edge
of clock.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend mode
or Self Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
Separated power from V
improve noise.
Separated ground from V
improve noise.
Publication Release Date:Aug. 13, 2007
DESCRIPTION
CC
SS
, used for output buffers to
, used for output buffers to
W9812G6GH
-Revision A06