AT45DB321-CC ATMEL [ATMEL Corporation], AT45DB321-CC Datasheet
AT45DB321-CC
Related parts for AT45DB321-CC
AT45DB321-CC Summary of contents
Page 1
... The AT45DB321 is a 2.7-volt only, serial interface Flash memory suitable for in-sys- tem reprogramming. Its 34,603,008 bits of memory are organized as 8192 pages of 528 bytes each. In addition to the main memory, the AT45DB321 also contains two SRAM data buffers of 528 bytes each. The buffers allow receiving of data while a page in the main memory is being reprogrammed ...
Page 2
... AT45DB321 2 To allow for simple in-system reprogrammability, the AT45DB321 does not require high input voltages for pro- gramming. The device operates from a single power sup operations. The AT45DB321 is enabled through the chip ...
Page 3
... To start a page read, the 8-bit opcode, 52H, is followed by 24 address bits and 32 don’t care bits. In the AT45DB321, the first address bit is reserved for larger density devices (see Notes on page 10), the next 13 address bits (PA12-PA0) ...
Page 4
... When a low to high transition occurs on the CS pin, the part will first erase the selected page in AT45DB321 4 main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. Both ...
Page 5
... When a low to high transition occurs on the CS pin, the part will first trans- fer data from the page in main memory to a buffer and then PA8 PA7 PA6 ...
Page 6
... The device density is indicated using bits 5, 4, and 3 of the status register. For the AT45DB321, the three bits are 1, 1, and 0. The decimal value of these three binary bits does not equate to the device density; the three bits represent a ...
Page 7
... This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT45DB321 - 2.7V to 3.6V 7 ...
Page 8
... Block Erase Time BE t RESET Pulse Width RST t RESET Recovery Time REC Input Test Waveforms and Measurement Levels 2.4V AC DRIVING LEVELS 0.45V < (10 AT45DB321 8 Condition CS, RESET all inputs IH at CMOS levels MHz mA; OUT CMOS levels IN ...
Page 9
AC Waveforms Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low when CS makes a high- to-low transition, and Waveform 2 shows the SCK signal being high when CS makes a high-to-low transition. Both ...
Page 10
... It is recommended that “r” logical “0” for densities of 32M bit or smaller. 3. For densities larger than 32M bit, the “r” bits become the most significant Page Address bit for the appropriate density. AT45DB321 10 CMD 8 bits 8 bits ...
Page 11
... Main Memory Page Program through Buffers PA12-6 CMD Buffer Write CS SI CMD Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page Each transition represents 8 bits and 8 clock cycles FLASH MEMORY ARRAY MAIN MEMORY PAGE PROGRAM THROUGH BUFFER 2 ...
Page 12
... Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer Buffer Read Each transition represents 8 bits and 8 clock cycles AT45DB321 12 FLASH MEMORY ARRAY MAIN MEMORY PAGE READ I/O INTERFACE SO PA5-0, BA9-8 BA7-0 X Starts reading page data into buffer ...
Page 13
... Detailed Bit-Level Read Timing – Inactive Clock Polarity Low Main Memory Page Read CS SCK 1 2 tSU COMMAND OPCODE Buffer Read CS SCK 1 2 tSU COMMAND OPCODE Status Register Read CS SCK 1 2 tSU HIGH-IMPEDANCE ...
Page 14
... COMMAND OPCODE Buffer Read CS SCK 1 2 tSU COMMAND OPCODE Status Register Read CS SCK tSU HIGH-IMPEDANCE SO AT45DB321 HIGH-IMPEDANCE HIGH-IMPEDANCE COMMAND OPCODE ...
Page 15
... PA3 PA2 PA2 PA1 PA1 PA0 PA0 Main Memory Main Memory Page to Buffer 1 Page to Buffer 2 Compare Compare 60H 61H PA12 PA12 PA11 ...
Page 16
... PA0 PA0 AT45DB321 16 Buffer 2 to Main Memory Page Program without Built-In Page Block Erase Erase Erase Opcode 89H 81H 50H ...
Page 17
... This type of algorithm is used for applications in which an entire sector is programmed sequentially, filling the sector page- by-page page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire sector ...
Page 18
... AT45DB321 18 START provide address of page to modify MAIN MEMORY PAGE to BUFFER TRANSFER (53H, 55H) BUFFER WRITE (84H, 87H) (82H, 85H) BUFFER to MAIN MEMORY PAGE PROGRAM (83H, 86H) (2) Auto Page Rewrite (58H, 59H) ...
Page 19
... SCK 32T 32-Lead, Plastic Thin Small Outline Package (TSOP) 24C3 24-Ball Array Plastic Chip-Scale Ball Grid Array (CBGA) Standby Ordering Code 0.01 AT45DB321-TC AT45DB321-CC 0.01 AT45DB321-TI AT45DB321-CI Package Type Package Operation Range 32T Commercial 24C3 ( 32T Industrial 24C3 ...
Page 20
Packaging Information 32T, 32-Lead, Plastic Thin Small Outline Package (TSOP) Dimensions in Millimeters and (Inches)* JEDEC OUTLINE MO-142 BD INDEX MARK 18.5(.728) 18.3(.720) 0.50(.020) 0.25(.010) BSC 7.50(.295) 0.15(.006) REF 8.20(.323) 7.80(.307) 0.15(.006) 0.05(.002 REF 0.70(.028) 0.50(.020) *Controlling dimension: ...