AT45DB321-CC ATMEL [ATMEL Corporation], AT45DB321-CC Datasheet - Page 3

• Manufacturer Part Number: AT45DB321-CC
• Description: 32-Megabit 2.7-volt Only Serial DataFlash
• Manufacturer: ATMEL [ATMEL Corporation]

Memory Architecture Diagram
Device Operation
The device operation is controlled by instructions from the
host processor. The list of instructions and their associated
opcodes are contained in Table 1 and Table 2. A valid
instruction starts with the falling edge of CS followed by the
appropriate 8-bit opcode and the desired buffer or main
memory address location. While the CS pin is low, toggling
the SCK pin controls the loading of the opcode and the
desired buffer or main memory address location through
the SI (serial input) pin. All instructions, addresses, and
data are transferred with the most significant bit (MSB) first.
Read
By specifying the appropriate opcode, data can be read
from the main memory or from either one of the two data
buffers.
MAIN MEMORY PAGE READ: A main memory read allows
the user to read data directly from any one of the 8192
pages in the main memory, bypassing both of the data buff-
ers and leaving the contents of the buffers unchanged. To
start a page read, the 8-bit opcode, 52H, is followed by 24
address bits and 32 don’t care bits. In the AT45DB321, the
first address bit is reserved for larger density devices (see
Notes on page 10), the next 13 address bits (PA12-PA0)
specify the page address, and the next 10 address bits
(BA9-BA0) specify the starting byte address within the
SECTOR ARCHITECTURE
SECTOR 1 = 261,888 bytes (248K + 7936)
SECTOR 15 = 270,336 bytes (256K + 8K)
SECTOR 16 = 270,336 bytes (256K + 8K)
SECTOR 2 = 270,336 bytes (256K + 8K)
SECTOR 0 = 4224 bytes (4K + 128)
SECTOR 0
BLOCK ARCHITECTURE
Block = 4224 bytes
BLOCK 1022
BLOCK 1023
BLOCK 126
BLOCK 127
BLOCK 128
BLOCK 129
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
BLOCK 0
BLOCK 1
BLOCK 2
(4K + 128)
page. The 32 don’t care bits which follow the 24 address
bits are sent to initialize the read operation. Following the
32 don’t care bits, additional pulses on SCK result in serial
data being output on the SO (serial output) pin. The CS pin
must remain low during the loading of the opcode, the
address bits, and the reading of data. When the end of a
page in main memory is reached during a main memory
page read, the device will continue reading at the beginning
of the same page. A low to high transition on the CS pin will
terminate the read operation and tri-state the SO pin.
BUFFER READ: Data can be read from either one of the
two buffers, using different opcodes to specify which buffer
to read from. An opcode of 54H is used to read data from
buffer 1, and an opcode of 56H is used to read data from
buffer 2. To perform a buffer read, the eight bits of the
opcode must be followed by 14 don’t care bits, 10 address
bits, and eight don't care bits. Since the buffer size is 528-
bytes, 10 address bits (BFA9-BFA0) are required to specify
the first byte of data to be read from the buffer. The CS pin
must remain low during the loading of the opcode, the
address bits, the don’t care bits, and the reading of data.
When the end of a buffer is reached, the device will con-
tinue reading back at the beginning of the buffer. A low to
high transition on the CS pin will terminate the read opera-
tion and tri-state the SO pin.
8 Pages
PAGE ARCHITECTURE
Page = 528 bytes
PAGE 8189
PAGE 8190
PAGE 8191
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
(512 + 16)
3