STK14CA8-N25I ETC [List of Unclassifed Manufacturers], STK14CA8-N25I Datasheet - Page 11

• Manufacturer Part Number: STK14CA8-N25I
• Description: 128K x 8 AutoStoreTM nvSRAM QuantumTrapTM CMOS Nonvolatile Static RAM
• Manufacturer: ETC [List of Unclassifed Manufacturers]

nvSRAM
SRAM READ
The STK14CA8 nvSRAM is made up of two
functional components paired in the same physical
cell. These are a SRAM memory cell and a
nonvolatile
cell operates as a standard fast static RAM. Data in
the SRAM can be transferred to the nonvolatile cell
(the STORE operation), or from the nonvolatile cell
to SRAM (the RECALL operation). This unique
architecture allows all cells to be stored and recalled
in parallel. During the STORE and RECALL
operations SRAM READ and WRITE operations are
inhibited. The STK14CA8 supports unlimited reads
and writes just like a typical SRAM. In addition, it
provides unlimited RECALL operations
nonvolatile cells and up to 1 million STORE
operations.
The STK14CA8 performs a READ cycle whenever
The address specified on pins A
of the 131,072 data bytes will be accessed. When the
READ is initiated by an address transition, the
outputs will be valid after a delay of t
cycle #1). If the READ is initiated by
outputs will be valid at t
later (READ cycle #2). The data outputs will
repeatedly respond to address changes within the
t
any control input pins, and will remain valid until
another address change or until
high, or
December 2004
AVQV
E
and
access time without the need for transitions on
W
G
Figure 4:
QuantumTrap™ cell
or
are low while
HSB
V
CAP
AutoStore
is brought low.
ELQV
V
or at t
W
TM
W
CC
. The SRAM memory
Mode
16-0
and
E
GLQV
determines which
or
DEVICE OPERATION
HSB
, whichever is
E
G
AVQV
or
is brought
V
are high.
from the
CC
G
(READ
, the
SRAM WRITE
A WRITE cycle is performed whenever
are low and
stable prior to entering the WRITE cycle and must
remain stable until either
end of the cycle. The data on the common I/O pins
DQ
before the end of a
before the end of an
It is recommended that
entire WRITE cycle to avoid data bus contention on
common I/O lines. If
turn off the output buffers t
AutoStore™ OPERATION
The STK14CA8 stores data to nvSRAM using one of
three storage operations. These three operations are
Hardware Store, activated by
actived by an address sequence, and AutoStore™, on
device power down.
AutoStore™ operation is a unique feature of Simtek
QuantumTrap™ technology and is enabled by default
on the STK14CA8.
During normal operation, the device will draw current
from Vcc to charge a capacitor connected to the Vcap
pin. This stored charge will be used by the chip to
perform a single STORE operation. If the voltage on
the Vcc pin drops below Vswitch, the part will
automatically disconnect the Vcap pin from Vcc. A
STORE operation will be initiated with power provided
by the Vcap capacitor.
Figure 4 shows the proper connection of the storage
capacitor (Vcap) for automatic store operation. Refer
to the DC CHARACTERISTICS table for the size of
Vcap. The voltage on the Vcap pin is driven to 5V by a
charge pump internal to the chip. A pull up should be
placed on
To reduce unneeded nonvolatile stores, AutoStore™
and Hardware Store operations will be ignored unless
at least one WRITE operation has taken place since
the most recent STORE or RECALL cycle. Software
initiated STORE cycles are performed regardless of
whether a WRITE operation has taken place. The
an AutoStore™ cycle is in progress.
HSB
11
0-7
signal can be monitored by the system to detect
will be written into the memory if it is valid t
W
HSB
Document Control #ML0022 rev 1.0
to hold it inactive during power up.
is high. The address inputs must be
E
G
W
controlled WRITE.
is left low, internal circuitry will
G
WLQZ
controlled WRITE or t
E
be kept high during the
or
after
HSB ,
W
goes high at the
W
Software Store,
goes low.
STK14CA8
E
and
DVWH
DVEH
W