W25P10 WINBOND [Winbond], W25P10 Datasheet
W25P10
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W25P10 Summary of contents
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... AND 4M-BIT SERIAL FLASH MEMORY WITH 40MHZ SPI Formally NexFlash NX25P10, NX25P20 and NX25P40 The Winbond W25P10/20/40 are fully compatible with the previous NexFlash NX25P10/20/40 Serial Flash memories. W25P10, W25P20 AND W25P40 Publication Release Date: November 28, 2005 - 1 - Revision M ...
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... Status Register Memory Protection ................................................................................11 7.2 INSTRUCTIONS........................................................................................................... 11 7.2.1 Manufacturer and Device Identification...........................................................................12 7.2.2 Instruction Set 7.2.3 Write Disable (04h).........................................................................................................13 7.2.4 Write Enable (06h)..........................................................................................................13 7.2.5 Read Status Register (05h) ............................................................................................14 7.2.6 Write Status Register (01h) ............................................................................................15 7.2.7 Read Data (03h) .............................................................................................................16 7.2.8 Fast Read (0Bh) .............................................................................................................17 7.2.9 Page Program (02h) .......................................................................................................18 7.2.10 Sector Erase (D8h).......................................................................................................19 W25P10, W25P20 AND W25P40 (1) ............................................................................................................. ...
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... AC Electrical Characteristics ........................................................................................ 29 8.7 AC Electrical Characteristics (cont’d) ........................................................................... 30 8.8 Serial Output Timing ..................................................................................................... 31 8.9 Input Timing .................................................................................................................. 31 8.10 Hold Timing................................................................................................................... 31 9. PACKAGE SPECIFICATION .................................................................................................... 32 9.1 8-Pin SOIC 150-mil (Winbond Package Code SN) (NexFlash Package Code N) ....... 32 10. ORDERING INFORMATION .................................................................................................... 33 11. REVISION HISTORY ................................................................................................................ 34 W25P10, W25P20 AND W25P40 Publication Release Date: November 28, 2005 - 3 - Revision M ...
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... As part of a family of Serial Flash products, Winbond also provides a compatible migration path to 8M/16M/32M-bit densities. The W25P10/20/40 array is organized into 512/1024/2048 programmable pages of 256-bytes each. A single byte or 256 bytes, can be programmed at a time using the Page Program instruction. Pages are grouped into 2/4/8 erasable sectors of 256 pages (64K-byte) each as shown in figure 2. ...
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... Package Types The standard package for the W25P10/20/ 8-pin plastic SOIC with 150-mil body (Winbond package code SN) (NexFlash package code N). It also allows a package migration path to higher density Serial Flash devices. The pinout for the package is shown in Figure 1. Package diagrams and dimensions are illustrated at the end of this data sheet ...
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... The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI "Operations") 4.7 Serial Data Input (DI) The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK) input pin. W25P10, W25P20 AND W25P40 - 6 - ...
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... BLOCK DIAGRAM Figure 2. W25P10, W25P20 and W25P40 Block Diagram W25P10, W25P20 AND W25P40 Publication Release Date: November 28, 2005 - 7 - Revision M ...
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... Hold Function The /HOLD signal allows the W25P10/20/40 operation to be paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are shared with other devices. For example, consider if the page buffer was only partially written when a priority interrupt requires use of the SPI bus ...
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... Upon power- power-down the W25P10/20/40 will maintain a reset condition while VCC is below the threshold value of V reset, all operations are disabled and no instructions are recognized. During power-up and after the VCC voltage exceeds V , all program and erase related instructions are further disabled for a time WI ...
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... The factory default setting for the Block Protection Bits is 0, none of the array protected. The Block Protect bits can not be written to if the Status Register Protect (SRP) bit is set to 1 and the Write Protect (/WP) pin is low. The W25P20 and W25P10 do not use BP2. 7.1.4 Reserved Bits Status register bit locations 5 and 6 are reserved for future use ...
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... INSTRUCTIONS The instruction set of the W25P10/20/40 consists of twelve basic instructions that are fully controlled through the SPI bus (see Instruction Set table). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first ...
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... The Device ID will repeat continuously until /CS terminates the instruction. 4. The Manufacturer ID and Device ID bytes will repeat continuously until /CS terminates the instruction. 5. Unused upper address bits must be set for the W25P10. 6. The lowest 16 address bits (A15-A0) must be set to 0. W25P10, W25P20 AND W25P40 ...
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... DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, and Chip Erase instructions. Figure 5. Write Enable Instruction Sequence Diagram W25P10, W25P20 AND W25P40 Publication Release Date: November 28, 2005 - 13 - Revision M ...
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... Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. The Status Register can be read continuously, as shown in Figure 6. The instruction is completed by driving /CS high. Figure 6. Read Status Register Instruction Sequence Diagram W25P10, W25P20 AND W25P40 - 14 - ...
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... When the SRP pin is set the Write Status Register instruction is locked out while the /WP pin is low. When the /WP pin is high the Write Status Register instruction is allowed. Figure 7. Write Status Register Instruction Sequence Diagram W25P10, W25P20 AND W25P40 (See AC Characteristics). While W Publication Release Date: November 28, 2005 ...
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... Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Data instruction allows clock rates from D. maximum of f (see AC Electrical Characteristics). R W25P10, W25P20 AND W25P40 Figure 8. Read Data Instruction Sequence Diagram - 16 - ...
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... The dummy byte data value on the DI pin is a “don’t care”. Figure 9. Fast Read Instruction Sequence Diagram W25P10, W25P20 AND W25P40 (see AC Electrical Characteristics). This is accomplished by adding a R Publication Release Date: November 28, 2005 ...
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... After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (BP2, BP1, BP0) bits (see Status Register Memory Protection table). Figure 10. Page Program Instruction Sequence Diagram W25P10, W25P20 AND W25P40 - 18 - ...
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... Erase instruction will not be executed if the addressed page is protected by the Block Protect (BP2, BP1, BP0) bits (see Status Register Memory Protection table). Figure 11. Sector Erase Instruction Sequence Diagram W25P10, W25P20 AND W25P40 (See AC Characteristics). While the Sector SE Publication Release Date: November 28, 2005 ...
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... Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed if any page is protected by the Block Protect (BP2, BP1, BP0) bits (see Status Register Memory Protection table). Figure 12. Chip Erase Instruction Sequence Diagram W25P10, W25P20 AND W25P40 (See AC Characteristics). While the Chip Erase cycle ...
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... Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1. Figure 13. Deep Power-down Instruction Sequence Diagram W25P10, W25P20 AND W25P40 (See AC Characteristics). While in the power-down state only the Publication Release Date: November 28, 2005 ...
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... Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 15. The Device ID values for the W25P10, W25P20, and W25P40 are listed in the Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high ...
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... W25P10, W25P20 AND W25P40 Figure 15. Release Power-down / Device ID Instruction Sequence Diagram - 23 - Publication Release Date: November 28, 2005 Revision M ...
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... Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 16. The Device ID values for the W25P10, W25P20, and W25P40 are listed in the Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID ...
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... SYMBOL Supply Voltage (1) VCC Ambient Temperature Operating Note: 1. VCC voltage during Read can operate across the min and max range but should not exceed ±10% of the programming (erase/write) voltage. W25P10, W25P20 AND W25P40 (1) SYMBOL CONDITIONS VCC V Relative to Ground IO T STG T ...
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... Power-up Timing and Write Inhibit Threshold PARAMETER VCC (min) to /CS Low Time Delay Before Write Instruction Write Inhibit Threshold Voltage Note: 1. These parameters are characterized only. W25P10, W25P20 AND W25P40 SYMBOL t (1) VSL t (1) PUW V (1) WI Figure 17. Power-up Timing and Voltage Levels ...
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... IL Input High Voltage V IH Output Low Voltage V OL Output High Voltage V OH Notes: 1. See Preliminary Designation. 2. Tested on sample basis and specified through design and characterization data. TA=25° C, VCC 3V. W25P10, W25P20 AND W25P40 (1) CONDITIONS MIN ( (2) OUT /CS = VCC, VIN = GND or VCC ...
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... AC Measurement Conditions PARAMETER Load Capacitance Input Rise and Fall Times Input Pulse Voltages Output Timing Reference Voltages Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. W25P10, W25P20 AND W25P40 SYMBOL 0.2 VCC 0.3 VCC to UT Figure 18. AC Measurement I/O Waveform ...
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... Data In Hold Time /CS Active Hold Time relative to CLK (2.7V-3.6V / 3.0V-3.6V) /CS Not Active Setup Time relative to CLK /CS Deselect Time Output Disable Time Clock Low to Output Valid (2.7V-3.6V / 3.0V-3.6V) Output Hold Time /HOLD Active Setup Time relative to CLK (2.7V-3.6V / 3.0V-3.6V) W25P10, W25P20 AND W25P40 SYMBOL ALT MIN D.C. D. ...
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... Signature Read Write Status Register Cycle Time Page Program Cycle Time Sector Erase Cycle Time Chip Erase Cycle Time W25P10 and W25P20 Chip Erase Cycle Time W25P40 Notes: 1. Clock high + Clock low must be less than or equal to 1/f 2. Value guaranteed by design and/or characterization, not 100% tested in production. ...
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... Serial Output Timing 8.9 Input Timing 8.10 Hold Timing W25P10, W25P20 AND W25P40 Publication Release Date: November 28, 2005 - 31 - Revision M ...
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... BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within .0004 inches at the seating plane. W25P10, W25P20 AND W25P40 MILLIMETERS TYP. ...
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... ORDERING INFORMATION W25P10, W25P20 AND W25P40 Publication Release Date: November 28, 2005 - 33 - Revision M ...
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... M 11/28/05 W25P10, W25P20 AND W25P40 PAGE New Create Incorporated spiFlash trademark for W25P10, 20 and 40 product family. Adjusted data for consistency 10, 11, 14, 16, Adjusted pages for technical clarity. Updated 24 Special Options and Ordering Information MLP metal die pad notification; Under "Package Types," figure 3 and packaging information ...
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... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. The Winbond W25P10/20/40 are fully compatible with the previous NexFlash NX25P10/20/40 Serial Flash memories. W25P10, W25P20 AND W25P40 ...