COP424C NSC [National Semiconductor], COP424C Datasheet - Page 8

• Manufacturer Part Number: COP424C
• Description: Single-Chip 1k and 2k CMOS Microcontrollers
• Manufacturer: NSC [National Semiconductor]

Functional Description
The SIO register functions as a 4-bit serial-in serial-out shift
register for MICROWIRE I O and COPS peripherals or as a
binary counter (depending on the contents of the EN regis-
ter) Its contents can be exchanged with A
The XAS instruction copies C into the SKL latch In the
counter mode SK is the output of SKL in the shift register
mode SK outputs SKL ANDed with the clock
EN is an internal 4-bit register loaded by the LEI instruction
The state of each bit of this register selects or deselects the
particular feature associated with each bit of the EN regis-
ter
0 The least significant bit of the enable register EN0 se-
lects the SIO register as either a 4-bit shift register or a
4-bit binary counter With EN0 set SIO is an asynchro-
nous binary counter decrementing its value by one upon
FIGURE 3 Input Output Timing Diagrams (divide by 8 mode)
(Continued)
FIGURE 4 Microbus Read Operation Timing
FIGURE 5 Microbus Write Operation Timing
8
1 With EN1 set interrupt is enabled Immediately following
2 With EN2 set the L drivers are enabled to output the data
each low-going pulse (‘‘1’’ to ‘‘0’’) occurring on the SI
input Each pulse must be at least two instruction cycles
wide SK outputs the value of SKL The SO output equals
the value of EN3 With EN0 reset SIO is a serial shift
register left shifting 1 bit each instruction cycle time The
data present at SI goes into the least significant bit of
SIO SO can be enabled to output the most significant bit
of SIO each cycle time The SK outputs SKL ANDed with
the instruction cycle clock
an interrupt EN1 is reset to disable further interrupts
in Q to the L I O port Resetting EN2 disables the L driv-
ers placing the L I O port in a high-impedance input
state
TL DD 5259 – 5
TL DD 5259 – 6
TL DD 5259 – 4