LT3688 LINER [Linear Technology], LT3688 Datasheet - Page 22

• Manufacturer Part Number: LT3688
• Description: Dual 800mA Step-Down Switching Regulator with Power-On Reset
• Manufacturer: LINER [Linear Technology]

LT3688
APPLICATIONS INFORMATION
If WDO is low and RST goes low, then WDO will go
high. The WDE pin allows the user to turn on and off the
watchdog function. Leaving this pin open is okay and
will automatically enable the watchdog. It has an internal
weak pull-down to ground. The WDI pin has an internal
weak pull-up that keeps the WDI pin high. If watchdog is
disabled, leaving this pin open is acceptable.
Confi guration and Sequencing
Use the CONFIG pin to adjust the sequencing and the
behavior of the power-on reset and watchdog timers. The
table below shows all of the confi guration options.
Table 5.
CONDITION
Channel 1 starts before Channel 2
Channel 1 and Channel 2 start simultaneously
Watchdog operates only if Reset 1 Expires
Watchdog operates only if Reset 1 and Reset
2 Expire
RST1 and RST2 high only if Timer 1 Expires
RST1 and RST2 use independent timers
With the CONFIG pin tied high, V
shown in Figure 9a. After V
start increasing. In addition, the reset timer for Channel 1
starts. Once V
starts. Once the reset timers for both Channel 1 and Channel
2 have expired, the Watchdog will start operation.
With the CONFIG pin tied low, V
V
timer will only start if both V
as shown in Figure 9b. Once the reset timer programmed
by C
and the Watchdog will start operation. In this mode, tie
C
With the CONFIG pin open, V
simultaneously, as shown in fi gure 9c. After V
V
reaches V
the reset timer for Channel 1 has expired, the Watchdog
will start operation.
22
OUT1
POR2
UV
POR1
the reset timer for Channel 1 starts. Once V
reaches V
to GND.
Confi guration Options
UV
expires, both RST1 and RST2 can pull high,
, the reset timer for Channel 2 starts. Once
OUT2
UV
reaches V
, V
OUT2
will start increasing. The reset
UV
OUT1
OUT1
, the reset timer for Channel 2
OUT1
and V
OUT1
reaches V
OUT1
and V
OUT2
will rise fi rst. After
HIGH LOW OPEN
×
×
×
will rise fi rst, as
are above V
UV
OUT2
CONFIG
OUT1
, V
×
×
×
OUT2
can rise
reaches
OUT2
×
×
×
will
UV
,
Selecting the Reset Timing Capacitors
The reset timeout period is adjustable in order to
accommodate a variety of microprocessor applications.
The reset timeout period, t
a capacitor, C
value of this capacitor is determined by:
V
V
V
V
V
V
OUT1
OUT2
OUT1
OUT2
OUT1
OUT2
WDI (10V/DIV)
RST1 (5V/DIV)
RST2 (5V/DIV)
RST1 (5V/DIV)
RST2 (5V/DIV)
WDI (10V/DIV)
RST1 (5V/DIV)
RST2 (5V/DIV)
WDI (10V/DIV)
WDO (5V/DIV)
WDO (5V/DIV)
WDO (5V/DIV)
Figure 9. Startup Waveforms with the
Three Confi guration Settings
(10V/DIV)
(10V/DIV)
(10V/DIV)
(10V/DIV)
(10V/DIV)
(10V/DIV)
POR
Figure 9a. CONFIG = HIGH
Figure 9c. CONFIG = OPEN
, between the C
Figure 9b. CONFIG = LOW
RST
, is adjusted by connecting
10ms/DIV
10ms/DIV
10ms/DIV
POR
pin and ground. The
3688 F09c
3688 F09a
3688 F09b
3688f