S-8233BBFT SII [Seiko Instruments Inc], S-8233BBFT Datasheet - Page 18

• Manufacturer Part Number: S-8233BBFT
• Description: BATTERY PROTECTION IC (FOR A 3-SERIAL-CELL PACK)
• Manufacturer: SII [Seiko Instruments Inc]

18
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233B Series
Battery 2
Battery 3
Battery 1
Battery Protection IC Connection Example
[Description of Figure 9]
R11, R12, and R13 are used to adjust the battery conditioning current. The conditioning current during
over charge detection is given by Vcu (over charge detection voltage)/R (R: resistance). To disable the
conditioning function, open CD1, CD2, and CD3.
The over charge detection delay time (t
over current detection delay time (t
electrical characteristics.
R6 is a pull-up resistor that turns FET-B off when the COP terminal is opened. Connect a 100 kΩ to 1
MΩ resistor.
R5 is used to protect the IC if the charger is connected in reverse. Connect a 10 kΩ to 50 kΩ resistor.
If capacitor C6 is absent, rush current occurs when a capacitive load is connected and the IC enters the
over current mode. C6 must be connected to prevent it.
If capacitor C5 is not connected, the IC may enter the over discharge condition due to variations of
battery voltage when the over current occurs. In this case, a charger must be connected to return to the
normal condition. To prevent this, connect an at least 0.01 μF capacitor to C5.
If a leak current flows between the delay capacitor connection terminal (CCT, CDT, or COVT) and VSS,
the delay time increases and an error occurs. The leak current must be 100 nA or less.
Over discharge detection can be disabled by using FET-C. The FET-C off leak must be 0.1 μA or less.
If over discharge is inhibited by using this FET, the current consumption does not fall below 0.1 μA even
when the battery voltage drops and the IC enters the over discharge detection mode.
R1, R2, and R3 must be 1 kΩ or less.
R7 is the protection of the CTL when the CTL terminal voltage higher than V
to 5 kΩ resistor. If the CTL terminal voltage never greater than the V
without R7 resistance is allowed .
R12
R13
R1
R2
R3
R11
C3
C2
C1
FET1
FET2
FET3
FET-A
VCC
CD1
VC1
CD2
VC2
CD3
VSS
I0V1
DOP
) are changed with external capacitors (C4 to C6). See the
Seiko Instruments Inc.
CU1
to t
S-8233B series
FET-B
Figure 9
Nch open
drain
CU3
), over discharge detection delay time (t
COP
R6
1 MΩ
COVT
VMP
CCT
CTL
CDT
10 KΩ
CC
R5
voltage (ex. R7 connect to V
C4
C5
C6
CC
1 KΩ
R7
CTL logic is “normal” (S-8233BA)
CTL logic is “reverse” (S-8233BB)
Over charge delay
time setting
Over discharge delay
time setting
VSS(GND): Normal operation
Floating or VCC: Normal operation
voltage. Connect a 300 Ω
Floating or VCC: Inhibit charging
VSS(GND): Inhibit charging and
Over current delay
time setting
EB+
discharging.
EB -
discharge detection.
and discharging.
High: Inhibit over
FET-C
DD1
Rev.4.2
to t
DD3
), and
SS
_00
),