LT3694 LINER [Linear Technology], LT3694 Datasheet

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... Schottky catch diode to protect the LT3694 against short-circuit conditions. Frequency foldback and thermal shutdown provide additional protection. With its wide input voltage range 36V, the LT3694 regulates a broad array of power sources from 4-cell batteries and 5V logic rails to unregulated wall transformers, lead acid batteries and distributed power supplies ...

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... DRV2 UFD PACKAGE 28-LEAD (4mm 5mm) PLASTIC QFN θ = 34°C/W JA EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB LT3694-1 PINOUT IS SHOWN IN PARENTHESIS ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL LT3694EUFD#PBF LT3694EUFD#TRPBF LT3694IUFD#PBF LT3694IUFD#TRPBF LT3694EFE#PBF LT3694EFE#TRPBF LT3694IFE#PBF LT3694IFE#TRPBF ...

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... PGOOD PGOOD (Note 0. 0. 36V IN (Note 4) (Note 3) 10% Duty Cycle SW1 SW1 I = 100mA BST V – 36V BST BIAS LT3694/LT3694-1 MIN TYP MAX UNITS l 3.5 3 3.5 mA 0.1 2 μA 350 500 mV l 1.16 1.2 1.23 V ...

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... Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3694I is guaranteed to meet performance specifications from –40°C to 125°C junction temperature. Note 3: Current limit is guaranteed by design and/or correlation to static test ...

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... SWITCH DUTY CYCLE (%) Frequency 3.0 2.5 2.0 1.5 1.0 0 100 150 150 R (k) T LT3694/LT3694 12V 25°C, unless otherwise noted BST Pin Current vs Switch Current SWITCH CURRENT (A) 36941 G02 Switch Minimum On-Time and Off-Time vs Temperature ...

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... LT3694/LT3694-1 TYPICAL PERFORMANCE CHARACTERISTICS I vs Temperature TRK/SS 4.0 3.5 3.0 2.5 2.0 – 100 TEMPERATURE (°C) 36941 G10 LDO Current Limit vs Temperature –1 –2 –3 –4 –5 – 100 TEMPERATURE (°C) 36941 G13 LDO Minimum BIAS to DRV Voltage vs DRV Current 0 ...

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... LT3694’s internal reference and start-up circuitry. This pin must be locally bypassed. EN/UVLO (Pin 2/Pin 1): The EN/UVLO pin is used to shut down the LT3694. It can be driven from a logic level or used as an undervoltage lockout by connecting a resistor divider from V . ...

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... TRK/SS2 OUT2 + SD + 0.75V FB2 – 0.68V SLOPE COMP CLK GND Figure 1. LT3694 Block Diagram with Typical External Components 8 RT SYNC CLKOUT (LT3694) (LT3694-1) CLK + OVERVOLTAGE INT REG MASTER SHUTDOWN AND REF OSC – – THERMAL + SHUTDOWN LDO ...

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... Operation can be best understood by referring to the Block Diagram (Figure 1). If the EN/UVLO pin is below 0.35V (min), the LT3694 is shut down and draws <2μA from the input source tied the EN/UVLO pin is driven above 0.5V (typ), the ...

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... However, unlike most fixed frequency OFF(MIN) SW regulators, the LT3694 will not switch off at the end of 10 each clock cycle if there is sufficient voltage across the boost capacitor (C3 in Figure 1) to fully saturate the output switch. A forced switch off for a minimum time will only occur at the end of a clock cycle when the boost capaci- tor needs to be recharged ...

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... RT pin to ground forcing a clock signal into the SYNC pin (LT3694 only). The LT3694 applies a voltage of 0.75V across this resistor and uses the current to set the oscillator speed. The switching frequency is given by the following formula: 49 ...

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... The input Würth Elektronik capacitor is required to reduce the resulting voltage www.we-online.com ripple at the LT3694 and to force this very high frequency Coilcraft switching current into a tight local loop, minimizing EMI. www.coilcraft.com A 10μF capacitor is capable of this task, but only Sumida www ...

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... OUT LT3694/LT3694-1 The low ESR and small size of ceramic capacitors make them the preferred type for LT3694 applications. Not all ceramic capacitors are the same, however. Many of the higher value capacitors use poor dielectrics with high temperature and voltage coefficients. In particular, Y5V and Z5U types lose a large fraction of their capacitance with applied voltage and at temperature extremes ...

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... The LT3694 uses current mode control to regulate the output. This simplifies loop compensation. In particular, the LT3694 does not require the ESR of the output capacitor for stability, so the user is free to employ ceramic capacitors to achieve low output ripple and small circuit size. Frequency ...

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... V OUT 100mV/DIV I L 1A/DIV 100μs/DIV Figure 3. Transient Load Response of the LT3694 Front Page Application as the Load Current Is Stepped from 1A to 2.6A 3.3V OUT BST and BIAS Pin Considerations Capacitor C3 and the internal boost Schottky diode (see the Block Diagram in Figure 1) are used to generate a boost voltage that is higher than the input voltage. In most cases a 0.22μ ...

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... For proper start-up, the minimum input voltage is also limited by the boost circuit. If the input voltage is ramped slowly, or the LT3694 is turned on with its EN/UVLO or TRK/SS pin when the output is already in regulation, then the boost capacitor may not be fully charged. Because the boost capacitor is ...

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... APPLICATIONS INFORMATION Once EN/UVLO climbs above the first threshold, the inter- nal circuitry of the LT3694 is turned on but the switching regulator and LDOs remain shut off. A 2μA current sink on the EN/UVLO pin is activated to provide hysteresis for the programmable undervoltage function. The second threshold is an accurate 1.2V derived from the internal reference. When EN/UVLO is above the second threshold, the regulators turn on and the 2μ ...

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... FB pin will clamp at about 1.25V and the LDO will shut off reducing power consumption. This pull-up can be sourced from one of the LT3694 outputs provided that channel is always on when the other channels are on. The output stage of the LDO will drive the NPN base from the BIAS voltage least 1 ...

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... If an inductor is chosen that will not saturate excessively, an LT3694 buck regulator will tolerate a shorted output. There is another situation to consider in systems where the output will be held high when the input to the LT3694 is absent. This may occur in battery charging applications or in battery backup systems where a battery or some other supply is diode ORed with the LT3694’ ...

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... With 100 LFPM airflow, this resist- JA ance can fall by another 25%. Further increases in airflow will lead to lower thermal resistance. Because of the large output current capability of the LT3694, ). The loop possible to dissipate enough heat to raise the junc- tion temperature beyond the absolute maximum. When ...

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... THERMAL VIAS TO GROUND PLANE SIGNAL VIAS TO INNER LAYERS Figure 9. A Good PCB Layout Ensures Proper, Low EMI Operation PCB BOTTOM SIDE IS A SOLID GROUND PLANE VIAS TO LIM2/LIM3 VIAS TO BIAS VIAS TO Q2 COLLECTOR LT3694/LT3694-1 GND C V OUT1 OUT1 R LIM2 R LIM3 Q3 ...

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... TRANSIENT TO 70V UVLO 5.8V 1nF 0.1Ω OUT1 ZXTN25012EZ OUT2 2.5V 450mA 2.2μF 22 100k 4.7μF 26.7k V EN/UVLO BIAS BST IN TRK/SS1 SW TRK/SS2 TRK/SS3 DA FB1 LIM2 DRV2 V LT3694 C1 LIM3 24.9k DRV3 FB2 SYNC 10.7k PGOOD FB3 16k RT GND 36941 TA02 f = 2MHz SW 0.1μF 1.2μH OUT1 3.3V 1.7A B340A 34k 100pF 34k 10k 10μF 0.1Ω ...

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... CLKIN 10μF V EN/UVLO BIAS BST IN TRK/SS1 SW TRK/SS2 TRK/SS3 DA 1nF FB1 LIM2 V LT3694 C1 DRV2 LIM3 24.9k DRV3 FB2 SYNC 10.7k FB3 PGOOD 66.5k RT SYNC GND 36941 TA03 f = 800kHz SW LT3694/LT3694-1 0.22μF 5.4μH OUT1 5V 1.7A B340A 57.6k 10.2k 22μF 1000pF 20k 0.1Ω OUT1 ZXTN25020DG OUT3 3.3V 450mA 34k 2.2μF 10k 36941fa 23 ...

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... THE LDO OUTPUT CURRENT CAPABILITY IS LIMITED BY THE POWER DISSIPATION OF THE NPN PASS TRANSISTORS 24 Wide Input Range (6V to 36V) to 1.8V, 2.5V and 3.3V OUT2 22μF 100k 26.7k V EN/UVLO BIAS BST IN TRK/SS1 SW 4.7nF TRK/SS2 TRK/SS3 DA FB1 LT3694 LIM2 V C1 DRV2 LIM3 DRV3 34k 2.2μF FB2 PGOOD FB3 10k 90.2k RT SYNC GND 36941 TA04 f ...

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... ON THE TOP AND BOTTOM OF PACKAGE UFD Package 28-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1712 Rev B) 0.70 0.05 3.65 0.05 PACKAGE OUTLINE 3.50 REF 4.10 0.05 5.50 0.05 0.75 0.05 4.00 0.10 (2 SIDES) 3.50 REF 0.200 REF 0.00 – 0.05 LT3694/LT3694-1 PIN 1 NOTCH 2.50 REF R = 0. 0.115 45 CHAMFER TYP TYP 27 28 0.40 0. 3.65 0.10 2.65 0.10 (UFD28) QFN 0506 REV B ...

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... LT3694/LT3694-1 PACKAGE DESCRIPTION 6.60 ±0.10 4.50 ±0.10 SEE NOTE 4 RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0.09 – 0.20 0.50 – 0.75 (.0035 – .0079) (.020 – .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE 26 FE Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev H) Exposed Pad Variation CB 3 ...

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... Corrected the Pin Configuration drawing and Package Description for the TSSOP package. Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. LT3694/LT3694-1 PAGE NUMBER 2 36941fa ...

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... Linear Technology Corporation 28 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 ● 200k 52.3k V EN/UVLO BIAS BST IN 0.1μF TRK/SS1 SW TRK/SS2 B340A TRK/SS3 DA FB1 270pF LT3694-1 30. LIM2 0.2Ω DRV2 LIM3 DRV3 ZXTN25012EZ FB2 14k CLKOUT FB3 PGOOD RT GND 10k f = 1MHz 40.2k SW 10μ ...