LM26001BMH NSC [National Semiconductor], LM26001BMH Datasheet - Page 11

• Manufacturer Part Number: LM26001BMH
• Description: 1.5A Switching Regulator with High Efficiency Sleep Mode
• Manufacturer: NSC [National Semiconductor]

FREQUENCY ADJUSTMENT AND SYNCHRONIZATION
The switching frequency of the LM26001B can be adjusted
between 150 kHz and 500 kHz using a single external resis-
tor. This resistor is connected from the FREQ pin to ground
as shown in the typical application. The resistor value can be
calculated with the following empirically derived equation:
The switching frequency can also be synchronized to an ex-
ternal clock signal using the SYNC pin. The SYNC pin allows
the operating frequency to be varied above and below the
nominal frequency setting. The adjustment range is from 30%
above nominal to 20% below nominal. External synchroniza-
tion requires a 1.2V (typical) peak signal level at the SYNC
pin. The FREQ resistor must always be connected to initialize
the nominal operating frequency. The operating frequency is
synchronized to the falling edge of the SYNC input. When
SYNC goes low, the high-side switch turns on. This allows
any duty cycle to be used for the sync signal when synchro-
nizing to a frequency higher than nominal. When synchroniz-
ing to a lower frequency, however, there is a minimum duty
cycle requirement for the SYNC signal, given in the equation
below:
Where fnom is the nominal switching frequency set by the
FREQ resistor, and fsync is a square wave. If the SYNC pin
is not used, it must be pulled low for normal operation. A
10kΩ pull-down resistor is recommended to protect against a
missing sync signal. Although the LM26001B is designed to
operate at up to 500 kHz, maximum load current may be lim-
ited at higher frequencies due to increased temperature rise.
See the Thermal Considerations section.
VBIAS
The VBIAS pin is used to bypass the internal regulator which
provides the bias voltage to the LM26001B. When the VBIAS
pin is connected to a voltage greater than 3V, the internal
regulator automatically switches over to the VBIAS input. This
reduces the current into VIN (Iq) and increases system effi-
ciency. Using the VBIAS pin has the added benefit of reducing
power dissipation within the device.
FIGURE 5. Swtiching Frequency vs R
R
FREQ
= (6.25 x 10
10
) x f
SW
-1.042
FREQ
30001951
11
For most applications where 3V < Vout < 10V, VBIAS can be
connected to Vout. If not used, VBIAS should be tied to GND.
If VBIAS drops below 2.9V (typical), the device automatically
switches over to supply the internal bias voltage from Vin.
Total device input current is the sum of Iq, gate drive current,
and VBIAS current, plus some negligible current into the FB
pin. Total minimum input supply current can be calculated as
shown below:
Where I
Total supply input current varies according to load, system
efficiency, and operating frequency. To calculate minimum
input current during sleep mode, use Iq
I
For input current in PWM mode, use the same equation, with
Iq
If VBIAS is connected to ground, use the same equation with
the Ibias term eliminated and either I
Iq
LOW VIN OPERATION AND UVLO
The LM26001B is designed to remain operational during short
line transients when input voltage may drop as low as 3.0V.
Minimum nominal operating input voltage is 4.0V. Below this
voltage, switch R
voltage from VDD. The minimum voltage required at VDD is
approximately 3.5V for normal operation within specification.
VDD can also be used as a pull-up voltage for functions such
as PGOOD and FPWM. Note that if VDD is used externally,
the pin is not recommended for loads greater than 1 mA.
If the input voltage approaches the nominal output voltage,
the duty cycle is maximized to hold up the output voltage. In
this mode of operation, once the duty cycle reaches its max-
imum, the LM26001B can skip a maximum of seven off puls-
es, effectively increasing the duty cycle and thus minimizing
the dropout from input to output. Typical off-pulse skipping
waveforms are shown below.
UVLO is sensed at both VIN and VDD, and is activated when
either voltage falls below 2.9V (typical). Although VDD is typ-
BIAS_SLEEP
_PWM_VB
_PWM_VDD
QG
FIGURE 6. Off-pulse Skipping Waveforms
Vin = 3.5V, Vnom = 3.3V, fnom = 305kHz
, and I
.
is the gate drive current, calculated as:
.
BIAS_PWM
DS(ON)
I
QG
= (4.6 x 10
increases, due to the lower gate drive
.
-9
) x f
SW
30001929
q_Sleep_VDD
_Sleep_VB
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