LM26001BMH NSC [National Semiconductor], LM26001BMH Datasheet - Page 12

• Manufacturer Part Number: LM26001BMH
• Description: 1.5A Switching Regulator with High Efficiency Sleep Mode
• Manufacturer: NSC [National Semiconductor]

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ically less than 200mV below VIN, it will not discharge through
VIN. Therefore when the VIN voltage drops rapidly, VDD may
remain high, especially in sleep mode. For fast line voltage
transients, using a larger capacitor at the VDD pin can help
to hold off a UVLO shutdown by extending the VDD discharge
time. By holding up VDD, a larger cap can also reduce the
R
nately, under heavy loading the VDD voltage can fall several
hundred mV below VIN. In this case, UVLO may be triggered
by VDD even though the VIN voltage is above the UVLO
threshold.
When UVLO is activated the LM26001B enters a standby
state in which VDD remains charged. As input voltage and
VDD voltage rise above 3.9V (typical) the device will restart
from softstart mode.
PGOOD
A power good pin, PGOOD, is available to monitor the output
voltage status. The pin is internally connected to an open
SETTING OUTPUT VOLTAGE
The output voltage is set by the ratio of a voltage divider at
the FB pin as shown in the typical application. The resistor
values can be determined by the following equation:
Where Vfb = 1.234V typically.
A maximum value of 150kΩ is recommended for the sum of
R1 and R2.
As input voltage decreases towards the nominal output volt-
age, the LM26001B can skip up to seven off-pulses as de-
scribed in the Low Vin Operation section. In low output voltage
applications, if the on-time reaches Ton
skip on-pulses to maintain regulation. There is no limit to the
number of pulses that are skipped. In this mode of operation,
however, output ripple voltage may increase slightly.
INDUCTOR
The output inductor should be selected based on inductor
ripple current. The amount of inductor ripple current com-
DS(ON)
(and dropout voltage) in low VIN conditions. Alter-
MIN
, the device will
FIGURE 7. Example Circuit
1.5A Max, 305 kHz
12
drain MOSFET, which remains open while the output voltage
is within operating range. PGOOD goes low (low impedance
to ground) when the output falls below 85% of nominal or EN
is pulled low. When the output voltage returns to within 92%
of nominal, as measured at the FB pin, PGOOD returns to a
high state. For improved noise immunity, there is a 5us delay
between the PGOOD threshold and the PGOOD pin going
low.
Design Information
EXAMPLE CIRCUIT
Figure 7 shows a complete typical application schematic. The
components have been selected based on the design criteria
given in the following sections.
pared to load current, or ripple content, is defined as Iripple/
Iload. Ripple content should be less than 40%. Inductor ripple
current, Iripple, can be calculated as shown below:
Larger ripple content increases losses in the inductor and re-
duces the effective current limit.
Larger inductance values result in lower output ripple voltage
and higher efficiency, but a slightly degraded transient re-
sponse. Lower inductance values allow for smaller case size,
but the increased ripple lowers the effective current limit
threshold.
Remember that inductor value also affects the sleep mode
threshold as shown in Figure 3.
When choosing the inductor, the saturation current rating
must be higher than the maximum peak inductor current and
the RMS current rating should be higher than the maximum
load current. Peak inductor current, Ipeak, is calculated as:
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